Should OCLK and CLK_LVDS have the same phase?

Knowledge Base Article # Q200124

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Summary I noticed that there was a significant phase difference between CLK_LVDS and OCLK. Shouldn't they have the same phase?
CLK_LVDS (J4-P4 and J4-P38) and OCLK (J3-P22) are sourced from different PLL outputs within the DIO's FPGA, so it is possible for them to have different frequencies and different phase settings. Even if the phase settings are the same for both clocks, the actual phase observed at the output will be different since the respective signal paths are quite different.  Due to the programmability of it, the OCLK goes thru added logic, such as dividers, delays and an external buffer IC. The LVDS clock exits the PLL and goes straight from the FPGA to the connector, resulting in a much shorter signal path.

WARNING:  The CLK_LVDS signal is driven directly from the FPGA.  Shorting the CLK_LVDS may cause damage to the FPGA device.

See Also:  Q200126
Article Date 12/2/2008
Keywords DIO, LVDS, OCLK, CLK_LVDS, GX5280 Series, GX5290 Series

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