Architecture

The GT-DIO supports up to 25MHz (GT25) or up to 50MHz (GT50) operation. Each board contains 32 I/O pins arranged in 4 groups of 8, each group having its own direction: input or output. The direction of each group can be changed for each and every step, either internally by command words or externally in an unsynchronized mode. Each GT-DIO board can be configured from 16K steps up to 1M behind each I/O pin.

The GT-DIO works as a state machine with three main states:  HALT, PAUSE and RUN. One of the modules in the board is the sequencer. The sequencer interprets commands stored in the memory array and controls the states machine. Two other memory arrays hold the output data and the input data. The sequencer controls the address of the memory arrays and thereby controls the flow when the board is in the RUN state.

External control provides CLK, strobe and I/O pin direction from an external source. The combination of the external bi-directional control and external clocking, strobing, and triggering provides the capability to fully synchronize with UUTs and to minimize initialization procedures. The board sequencer permits the creation of conditional and unconditional loops and branches to manipulate the output vectors. This provides the capability to generate indefinite stimulus vectors at the maximum test rate.

 

Architecture Diagram.gif

Architecture Diagram