The DIO sends output patterns to the IO Module connector on the rising edge of the Clock (CLK) signal. (See the figure below). The CLK rate can be programmed from 5Hz to 50MHz. The DIO captures input patterns from the IO Module connector on the rising edge of Strobe (STB). The Strobe signal is the frequency as the Clock signal.
The CLK signal (common to all boards) and the Sequencer control the Program Counter on the Master. The Program Counter contains the current data memory address. The program counter points to address zero after reset or after a halt command.
The timing diagram of the figure below displays CLK and Strobe signals. The DIO board can be driven using either internal or external clock sources. In internal mode, Strobe occurs Ts nanoseconds before the next clock (CLK) signal (10 nSec default). Ts can be set from 4 – 18 nanoseconds before the CLK signal. In the external mode, Clock or Strobe signals are provided externally. Internal clock and external strobe cannot be combined.
Signal Timing Diagram