Control and Data Memory can be configured with 256K to 32M steps. Control Memory is one byte wide. Data Memory is 4 bytes wide and is organized in 8 banks. In order to maximize use of available memory, memory depth (total number of steps) can be software reconfigured to two or four times the installed amount. However, the number of active channels will decrease to 16 (half width) or 8 (one-quarter width).
For example, if the installed memory is 128Mbytes, then it can be software configured as 32 channels wide by 32M steps deep (default), 16 channels by 64M or 8 channels by 128M.
For the GT5150, one Control Memory byte is used for every eight Data memory bytes. This remains true regardless of the configured memory width. This has major programming implications related to memory width as discussed below.
Depending on memory width, instructions must reside on step boundary multiples of 2, 4 or 8. Otherwise, instructions are ignored.
When the board is set for 32-channel (4-byte) width, control can change on even-numbered step boundaries (2 steps of 4 bytes).
When the board width is configured for 16-channel (2-byte, 2x depth) operation, control can change every fourth step (4 steps of 2 bytes), that is, on step boundaries that are multiples of four.
When the board width is configured for 8-channel (1-byte) operation (4x depth), control can change every eighth step (8 steps of 1 byte), that is, on step boundaries that are multiples of eight.
The rule is summarized in the table below:
Data Width |
Step Control Ratio |
32-bit |
Two steps per control memory byte. |
16-bit |
Four steps per control memory byte. |
8-bit |
Eight steps per control memory byte. |
Memory Boundary Rules
Each control byte contains four bits that enable/disable each of four 8-pin groups. That setting is applied to all steps sharing the same control byte. Therefore, pin enable/disable states persist for blocks of 2, 4 or 8 steps, depending on the memory width selected. Instructions are executed on the last step of a block.
This example demonstrates how step position is considered:
● The Program Counter is set to zero.
● The command byte in step 0 is set to 0xC1 (unconditional jump to the step whose address is in Register A). See the Software User's Guide for control microcode information. Output groups 0 and 1 are enabled while groups 2 and 3 are disabled.
● If the data width is 32 bits then the same instruction is applied to steps 0 and 1. Output groups 0 and 1 are enabled and groups 2 and 3 are disabled for both steps 0 and 1. The instruction is executed on step 1.
● If the data width is 16 bits then the same instruction is applied to steps 0 through 3. Output groups 0 and 1 are enabled while groups 2 and 3 are disabled for all four steps 0 through 3. The instruction is executed on step 3.
● If the data width is 8 bits then the same instruction is applied to steps 0 through 7. Output groups 0 and 1 are enabled while groups 2 and 3 are disabled for all eight steps 0 through 7. The instruction is executed on step 7.