The GX5055 can operate at frequencies up to 50MHz. Each board contains 32 I/O pins and each pin can be configured as an input or output on a per cycle basis. Each board has 512Ksteps behind each I/O pin. The GX5055 offers high performance pin electronics and an enhanced timing generator in a single-slot 6U PXI form factor. Each card can function as a stand-alone digital subsystem or if required, multiple cards can be interconnected, providing a single domain and supporting up to 512 bi-directional pins. Each digital pin can be individually programmed for a drive high, drive low, input threshold high, input threshold low, and a load value (with commutation voltage level) – offering the user complete flexibility when creating test programs and fixtures for multiple UUTs. Slew rate is also adjustable, providing further flexibility when creating and verifying test programs and fixtures. Each channel output can be formatted programmatically to one of the following formats: No Return, Return to Zero, Return to One, Return to Hi-Z, Return to Complement. Output formatting provides flexibility to create a variety of bus cycles and waveforms to test board and box level products. Each output channel can sense an over current sink or source condition, protecting each I/O channel from an overload condition. These conditions are recorded and the channel’s output will go to a HI-Z state until the over current flag is cleared.
The GX5055 includes 5 banks of 512Kby 32 memory, supporting drive, input, direction, control and data valid functionality for each channel.
The GX5055 functions as a state machine with three main states: HALT, PAUSE and RUN. One of the GX5055’s functional modules is the sequencer. The sequencer interprets commands stored in a memory array and controls the states machine. The sequencer controls the address of the memory arrays and thereby controls the flow when the board is in the RUN state.
External control signals include CLK, strobe and I/O pin direction. The combination of the external bi-directional control, external clocking, strobing, and triggering provides the capability to fully synchronize with UUTs, minimizing initialization procedures. The board sequencer permits the creation of conditional and unconditional loops and branches to manipulate the output vectors. This provides the capability to generate indefinite stimulus vectors at the maximum test rate.
Each channel has its own Parametric Measurement Unit (PMU). The PMU offers the ability to perform analog measurements on each digital pin. Measurement configurations include force voltage, measure current and force current, measure voltage.
Additionally, under software control, each channel’s operating temperature, Vcc / Vee voltage rails, drive high / drive low voltages, sense hi / sense lo voltages, and output current values can all be monitored and measured.
Each input channel’s source and sink load currents can be set programmatically. The input channel current source forces the specified constant current to be active when the input voltage is above the high voltage clamp value. Each input channel’s constant current voltage clamp can be set programmatically. With independent high and low clamping (commutating) voltages, the source and sink currents each have their own threshold voltage. Each input channel‘s load may be configured as a selectable resistor with pull-up and pull-down values or the value can be an open circuit. Each input channel’s high and low voltage threshold comparator delays can be set programmatically. Each output channel has independent adjustments for the rising and falling edge slew rates. Additionally, each output / input channel can be programmed to have a skew delay. These programmable delays are used as part of the GX5055’s deskew calibration routine and are not user accessible. Each output channel’s drive low and drive high voltages can be set programmatically. The total output driver voltage swing (output driver high voltage less output driver low voltage) is limited to 25V per channel.
The figure below presents a block diagram of the GX5055’s architecture.
Architecture Block Diagram