Output Data Block Diagram
The figure below is a block diagram of a single pin when operating in output mode. Up to 16 boards can be used in one domain for a maximum of 512 pins (each board containing 32 I/O pins). Output data, which is stored in the output memory is outputted from the board as a function of the CLK signal through the pin electronics when enabled. The direction memory enables the pin electronics output when the specified step is defined as an output step. The output data to the UUT will also be stored in the input memory via the receiver pin electronics. The output data will be formatted as it was defined programmatically by the user to one of the following formats: No Return, Return to Zero, Return to One, Return to Hi-Z, Return to Complement.
Each data channel’s output signal has programmable drive hi and drive lo levels. The drive hi level can be set from -9 volts to +15 volts and must be greater than the output driver’s drive lo voltage. The output driver’s drive lo voltage can be set from -10 volt to +11 volts. These levels are based on a Vcc voltage of +18 volts and a Vee voltage of -14 volts. Each output channel’s slew rate can be programmed, with rising and falling slew rates programmed independently.
Each output driver has over current protection. Once an over current condition occurs, the output will be set automatically to Hi-Z. The over current event can be monitored by the CPU as well as cleared by CPU control in order to enable the output.