The clock (CLK) signal initiates each output vector. The rate of this signal can be programmed from 5Hz to 50MHz. Similarly, the strobe signal latches the input vector. All clock and strobe signals are distributed to all DIOs (in the same Master/Slave domain) via the PXI local bus. The figure below presents a Clock Source Block Diagram.
Clock Source Block Diagram
The GX5055 has the following clock source signals:
1. Internal Programmable Clock – programmable clock from 5Hz to 50MHz with increments of 1Hz. See Specifications for details
2. External Clock – supplied by the user through J8 Timing Control connector. Input can be from 5Hz to 50MHz. See Specifications for details.
There are two clock signals generated by the timing resource located on the GX5055:
Clock |
The DIO clocks out output patterns to the IO connector on the rising edge of the Clock (CLK) signal. The Clock can have a delay of 0-63.75 ns (with increments of 0.25ns) relative to the clock source. |
Strobe |
The DIO captures input patterns from the IO connector on the rising edge of the Strobe (STB). When the Strobe source signal is internal, it has the same frequency as the Clock signal. The Strobe can have a delay of 0-63.75 ns (with programmable increments of 0.25ns) relative to the current clock source. |
A timing diagram of the CLK and Strobe signals is shown in the figure below.
Clock and Strobe Signal Timing Diagram