A DIO domain has one Master DIO board and up to seven DIO Slave boards. A DIO domain comprise of Master, its Slaves, Carriers and related modules. The figure below shows two domains from two different families on a PC bus.
Two Different DIO Domains on One PC Bus
Domains are internally synchronized and controlled through a Timing cable binding the Master’s Timing module to all domain Slave boards. To synchronize a domain with a UUT, you need to synchronize the Master board’s Timing module.
Masters and slaves within a domain must be members of the same product family. Each Slave adds 32 additional UUT I/O channels. Up to seven slaves can be added to a domain.
Full domain containing eight DIO boards provide up to 256 UUT I/O channels (256 channels wide). Because the driver supports 16 masters, up to 16 domains of mixed types can, in principle, share a computer bus. The number of master/slaves depends on the DIO Bus type (ISA, PXI, PCI), and the number of available free bus slots in your PC.
The following are key GX5152 characteristics and architecture:
● The GX5152 (Master), GX5153 (Slave) and GX5106 (Timing Control) are all Plug and Play (PnP) boards. The operating system such as Windows automatically identify and arbitrate resource requirements as well as notify the user that a new board was found and automatically install the driver for it.
● A DIO domain, when in RUN mode, operates independently of the host computer.
● Each GX5152 DIO board supports a maximum clock frequency of up to 50MHz per channel for all channels (total of 1.6GB of data per second). To use this clock rate, all SIMM modules in the domain must be rated at 50MHz
● A GX5152 (Master) board controls the timing of a DIO domain and can be synchronized to a UUT.
● Multiple Master boards are used to synchronize mutually asynchronous UUT elements.
● Each GX5153 (Slave) board adds up to 32 UUT channels. Up to 7 Slave boards can be added to make a total of 256-channel domain.
● DIO boards can support different interfaces (that is different voltage levels) by mounting different I/O Modules (see the I-O Modules and Interfaces User's Guide).
● Every GX5152 board, Master and Slave, require an I/O Module daughter card.
● All GX5152 channels of a specific board have the same direction. They are either all input or all output. Channel direction for individual boards in a domain can be different. Board direction can only be changed when the card is not running.
● GX5152 output channels can be enabled or disabled dynamically in groups of eight. Disabled channels on output boards are in Tri-State. This is useful for connecting to a user bus. Disabling the outputs has no effect if the board is set up for input.
● Configuration of board memories can vary within a domain. The board with the smallest step capacity limits the available number of vector steps (depth).
● The GX5152’s step (vector) capacity (depth) can be traded for channel capacity (width). The default width is 32 channels. Board depth depends on actual memory capacity. Depth can be increased by a factor of two or four with reduction in number of active channels by the same factor.
● Two registers, A and B, hold pre-defined jump addresses that can be loaded and triggered from the program. Additionally, register A jump addresses can be triggered from external source.
● The external Jump A signal can be programmed to trigger on transition (from '0' to '1') or level (triggers whenever pulled down).
● Triggers can be generated by external events on the Timing module External Event lines. Event and Mask registers are used to determine both the triggering event and the masking bits to be ignored. These use the D Event and Mask registers and T Event and Mask registers.
● External triggering can be initiated on sequential or concurrent events by using both D and T event registers to define events.
● The test sequence (vector) can be paused on external events unconditionally or conditionally. P Event and P Mask registers hold the condition and bits that generate a conditional pause.
● An X Register is used to emulate an external event condition under program control for purposes of test program verification. The register is loaded through the computer bus.
● A DIO domain can be set to have internal or external clock, in order to synchronize with the user UUT.
● A DIO domain clock source (internal or external), active when outputting data, can be programmatically delayed by 12-76 nSec (increments of 1nSec).
● A DIO domain Strobe source (internal or external), active when inputting data, can be programmatically delayed by 5-25 nSec (increments of 5nSec).
● All boards Firmware, GX5152, GX5153, GX5106 and I/O Modules can be upgraded through the DIO driver.
.gif "GX5152 DIO Board (GX5153 with four 256K SIMMs, GX5910, GX5106 and GX5101)")
GX5152 DIO Board (GX5153 with four 256K SIMMs, GX5910, GX5106 and GX5101)