Architecture

Introduction

The DIO-DSR Digital Stimulus/Response provides extensive high-speed digital test capability. Applications for the DIO-DSR include at-speed functional board testing, bus emulation, ASIC and PLD testing, and fast digital pattern generation and recording.

The DIO-DSR Digital Stimulus/Response Set consists of a single DIO-DSR Master and can be expanded to include up to additional seven DIO-DSR Slave boards. The DIO-DSR Master board consists of a Generator/Recorder board and 100MHz control/timing module.

Each DIO-DSR can be set as a Generator (Digital Stimulus) board or as a Recorder (Digital Response) board. Board’s settings can be changed intermittently using software. A DIO-DSR Generator/Recorder board has 32-channels I/O (all either inputs or outputs). Several UUT (unit under test) interfacing options are available by changing the DIO-DSR I/O module see the GX I-O Modules and Interfaces User's Guide (PXI) for details.

DIO DSR Operation

Each DIO-DSR module provides 32 digital outputs or 32 digital inputs channels with speed up to 50MHz/channel. Maximum channel depth for both input and output is 32Mbits/channel using pattern-looping capabilities output (generator) effective depth can be increased substantially. The output channels may be tri-stated in 8-bit groups, either internally through pattern control, or externally through tri-state control lines.

The major controlling element of the DIO-DSR system is the Major Cycle Controller that installed only the DIO-DSR Master board. This controller is an internal finite state machine that produces a repetitive sequence of events that control the DIO-DSR. One sequence can contain up to 256 unique states. Each state defines the logic level of each of the eight User Strobe Output lines, the test for the input flags, and the presence or absence of recorder and generator strobes. The fully programmable output strobes and input flags can continuously run at 100 MHz. Data is generated according to the clock patterns in the Major Cycle Memory and data is recorded according to the strobe patterns in the Major Cycle Memory. The Major Cycle also includes eight high-speed output strobes. These signals generate fast, repetitive, timing signals (e.g. address and data strobes in a bus emulation application). The Major Cycle high-speed input/output signals feature 10 ns edge placement resolution. The Major Cycle offers additional hardware control through external start with two qualifiers, external stop and trigger lines. An external clock allows both timing synchronization to other devices. The Major Cycle uses the internal Cross Trigger Bus for Start, Stop, and Trigger functions. This versatile capability allows interaction with other analog, digital, and switching modules.

The following introductory subtopics provide an overview of important architectural features. Later topics provide additional in-depth discussions.

DIIO-DSR Block Diagram

GX5152 Architecture Diagram