Major Cycle State Machine

The Major Cycle Timing Controller State Machine is of type sequential state machine, i.e. state machine that follow a finite sequence. In sequential machines an active state represent the state of the machine during the current iteration. The active state may change over time due to transition functions. Transitions are Boolean conditions that permit or deny entrance to the connecting state machine. Each state has an activity function associated with it that encompasses a specific behavior. The activity function computes a set of outputs, where an output is defined as a function of external input variables, local variables (static storage within the state machine) and software commands.

The Major Cycle State Machine provides a means for modeling the behavior of the DIO-DSR system by encapsulating the specific behavior for each specific condition.

The Major Cycle State Machine operates under three basic operational states: Halt, Pause and Run.

The figure below is a block diagram showing the relationship of these operational states and events.

 GX5152 Operational States

GX5152 Operational States

The State Machine run by the GX5106 Timing Controller board that mounted on top of the DIO-DSR Master board. The following table described in detail each state.

State

Description

Halt

The Halt state is the starting and end state of the DSR for every program. In this state only specific software Arm command will take the Major Cycle Timing Set Controller state machine to the Ready state.

The DIO board goes into a Halt state following:

  • Reset command

  • Major Cycle Sequencer was programmed to Halt at the end of Cycle

  • One of the Stop events coming from the Stop Logic circuit was met.

In this state all external control inputs are ignored, all events coming form Trigger/Start/Stop logic circuits are ignored. The Major Cycle, Recorder and Generator program counters are set to 0.

Ready

Intermittent state connecting between Halt and Pause states. The purpose of this state is to pipeline the sequence of events that lead to Pause/Run state. The only condition leading to this state is a valid Trigger input produced by the Trigger Logic circuit (see section for details). Form this state the state machines can advance to Pause state whenever a valid Start input produced by the Start Logic circuit (see section for details). Or back to Halt state if Reset/Halt command was issued.

Pause

The purpose of the Pause state is to freeze the current state of the State Machine settings and continuously check for conditions.

The state machine can either proceeds to Run or Halt states. A valid Trigger input produced by the Trigger Logic circuit (see section for details) would take the state machine to the Run state. A Reset/Halt command would set the state machine to the Halt state.

The state machine can only get to the Pause state from Run state if a Pause command was issued or Pause condition was generated by the sequencer logic circuit.

Pause command originates from the following sources:

  • Software (DIO driver function)

  • External control line (XPAUSE on J1) External Pause is activated when the external pause line goes low. This causes an immediate pause. The external pause condition overrides internally generated pause conditions.

  • Sequencer command

Run

The Run state is the natural operating mode. In this state the Major Cycle Controller produces a repetitive sequence of events that control all DIO-DSR boards, each sequence with up to 256 unique states. Each state output eight User Strobe Output lines, Boolean test for input flags and the presence or absence of recorder and generator strobes. Data is generated according to the clock patterns in the Major Cycle Timing Controller Memory and data is recorded according to the strobe patterns in the Major Cycle Timing Controller Memory.

Each step the Sequencer increments the Major Cycle Memory Program Counter by one unless the external Flags are not equal the current step flags Boolean equation. If not equal then the Major Cycle stay in the current address until it is. At the end of each Major Cycle the state can proceed to either Halt or Pause state if the Major Cycle Sequencer was programmed to do so.

The Major Cycle Sequencer will continue until one of the Stop conditions are met. Then it will advance to the Halt state.