Control and Data Memory can be configured with 256K to 32M steps. Control Memory is one byte wide. Data Memory is 4 bytes wide and is organized in 8 banks. In order to maximize use of available memory, memory depth (total number of steps) can be software reconfigured to two or four times the installed amount while the number of active channels decrease by the same amount.
For example, if the installed memory is 128Mbytes, then it can be software configured as 32 channels wide by 32M steps deep (default), 16 channels by 64M or 8 channels by 128M.
For the GX5150, one Control Memory byte is used for every eight Data memory bytes. This remains true regardless of the configured memory width. This has major programming implications related to memory width as discussed below.
Depending on memory width, instructions must reside on step boundary multiples of 2, 4 or 8. Otherwise, instructions are ignored.
When the board is set for 32-channel (4-byte) width, control can change on even-numbered step boundaries (2 steps of 4 bytes).
When the board width is configured for 16-channel (2-byte, 2x depth) operation, control can change every fourth step (4 steps of 2 bytes), that is, on step boundaries that are multiples of four.
When the board width is configured for 8-channel (1-byte) operation (4x depth), control can change every eighth step (8 steps of 1 byte), that is, on step boundaries that are multiples of eight.
This table summarized those rules:
Data Width |
Step Control Ratio |
32-bit |
Two steps per control memory byte. |
16-bit |
Four steps per control memory byte. |
8-bit |
Eight steps per control memory byte. |
Memory Boundary Rules
Step Control Ratio: Each Control memory byte controls a total of 8-bytes of data, a ratio of 8:1. The data can be arranged in two steps each 4-bytes wide, four steps each 2-bytes wide, or eight steps each 1-byte wide. This is the reason of having one bank memory for Control and eight banks memory for Data. |
Each control byte contains four bits that enable/disable each of four 8-pin groups. That setting is applied to all steps sharing the same control byte. Therefore, pin enable/disable states persist for blocks of 2, 4 or 8 steps, depending on the memory width selected. Instructions are executed on the last step of a block.
The number of steps that a single control byte controls depends on the memory width settings. The following example demonstrate that relationship:
● Program Counter is set to zero.
● Command (one byte) in step 0 is set to 0xC1:
● Command part (low 4-bits equal to 1) set to Jump A with no condition, i.e. an unconditional jump to the step whose address is in Register A. See the Software User's Guide and Programmer's Reference User's Guide for control micro code information.
Outputs Enable part (high 4-bits equal to 0xC): Groups 0 and 1 are enabled while groups 2 and 3 are disabled for output.
Data width is 32 bits |
The same instruction is applied to steps 0 and 1. Output groups 0 and 1 are enabled and groups 2 and 3 are disabled for both steps 0 and 1. The instruction is executed on step 1. |
Data width is 16 bits |
The same instruction is applied to steps 0 through 3. Output groups 0 and 1 are enabled while groups 2 and 3 are disabled for all four steps 0 through 3. The instruction is executed on step 3. |
Data width is 8 bits |
The same instruction is applied to steps 0 through 7. Output groups 0 and 1 are enabled while groups 2 and 3 are disabled for all eight steps 0 through 7. The instruction is executed on step 7. |