The clock (CLK) signal initiates each output vector. The rate of this signal can be programmed from 5Hz to 200MHz (depend on board model). Similarly, the strobe signal latches the input vector. All clock and strobe signals are distributed evenly to all DIOs.
Clock |
The DIO sends output patterns to the I/O connector on the rising edge of the Clock (CLK) signal. The Clock can have a delay of 0-25 nSec (with increments of 5) relative to the current clock source. |
Out Clock |
This clock signal has the same source and frequency as the Clock without time delay. |
Strobe |
The DIO captures input patterns from the I/O connector on the rising edge of Strobe (STB). When the Strobe source signal is internal, it has the same frequency as the Clock signal. The Clock can have a delay of 0-24 nSec (with increments of 5) relative to the current clock source. The timing diagram in the figure below displays CLK and Strobe signals. The DIO board can be driven using either internal or external clock sources. In internal mode, Strobe occurs Ts nanoseconds before the next clock (CLK) signal (10 nSec default). Ts can be set from 0 – 24 nanoseconds before the CLK signal. In the external mode, Clock or Strobe signals are provided externally. |
A timing diagram of the CLK and Strobe signals is shown in the figure below:
Signal Timing Diagram