The memory subsystem is composed of four blocks each of which can be separately configured as an input or an output. This configuration provides for presetting channels in groups of eight to either be input or output. All memories can be as large as 128Mb per channel with a sustained throughput of more than 100Mbits/Sec.
The memory subsystem is connected via the FPGA to the PXI bus at full bandwidth, for fast download or upload of vectors between the host computer and the GX5280.
Memory Management Block Diagram
The Clock/Strobe signals and the Vector Program Control the program counter that contains the address of the current I/O memory. After resetting, the program counter points to address zero and increments with the Clock/Strobe signals signal towards the last memory address.