GX5290e Specifications

Feature

Value

Timing

Internal Clock (PLL):

Range

GX5291e/GX5292e:

1 Hz (Min), 100 MHz (Max for all 32 I/O channels).

GX5293e:

1 Hz (Min), 100 MHz (Max for all 32 I/O channels).

1 Hz (Min), 200 MHz (Max with up to 16 I/O channels).

Resolution, max

Greater of 1Hz or 0.2%

Internal B Clock:

Range

1 to 200MHz

Resolution

0.2%

Internal Strobe Phase – Clock delay

1Hz<= Frequency <=100MHz:

0 – 27nS in 250pS steps

100MHz< Frequency <=200MHz:

0 – 3nS in 250pS steps

Ext.Test Clock

0 to 50MHz

Ext. Strobe

0 to 50MHz

Timing skew

1nS same card, 1nS between cards

Clock In

Direction

Input into Master board

Destinations

Reference clock (for the phase lock loop (PLL)

Sample clock

As Sample clock

Frequency range

3.5 MHz to 50 MHz

As Reference Clock

Reference clock frequency range

10 MHz ± 50 ppm

Input/Output

Data Direction control

Input or Output, fixed during execution

I/O channel width

32

Channels per board

32

Memory depth, steps

GX5291e: 32M

GX5292e/GX5293e: 64M

Trigger

Software, external override, or conditional

Pause

Software, external override, or conditional

External Status & Control

Output Enable

Tri-state in 8-pin groups

External Clock Enable

Internal, External and Select

Clock Output

As selected clock

External Strobe

As selected Input

External Event Bus

As selected 16 lines

Pause

As selected Override Input

Trigger

As selected Override Input

Run

As selected Indicator

B Clock

As selected Output

Environmental

Operating Temp.

0 to 50°C

Storage Temperature

-20 to 70°C

Physical Properties

Bus Interface

PXI Express

Dimensions

Single 3U PXI Express slot

Weight

Front Panel Connectors

Label:

J1

I/O TTL Signals, type 68-pin VHD connector

J2

I/O LVDS Signals, type 68-pin VHD connector (GX5292e/GX5293e)

J3

Timing Signals, type 68-pin VHD connector

J4

Control Connector, type 68-pin VHD connector