The following are key characteristics and features of the architecture:
● The GX5290/GX5290e is a Plug and Play (PnP) board. The operating system such as Windows automatically identifies and arbitrates resource requirements, notifies the user that a new board has been found and automatically installs the driver for it.
● A DIO domain operates independently of the host computer when in RUN mode.
● Each GX5290/GX5290e DIO board supports a maximum clock frequency of up to 200MHz (GX5293) per channel for all channels.
● A GX5290/GX5290e (Master) board controls the timing of its domain and can be synchronized to a UUT.
● Any GX5290/GX5290e board can be configured to be a Master or Slave, depending on the on-board switch settings (can only be done when the system is shutdown)
● Multiple Master boards are used to synchronize mutually asynchronous UUT elements.
● Each GX5290/GX5290e Slave board adds 32 UUT channels. Up to seven 15 boards can be added to make a total of 512-channel domain.
● Each channel can be enabled or disabled on a per vector basis. Disabled output channels will be in a tri-state mode – facilitating the testing or emulation of bi-directional busses.
● Each Master has a 16-bit external event bus. This bus is used for triggering and synchronizing with external events.
● Multiple trigger sources are available: Programmed PXI Trigger line, Star Trigger, External Trigger, Internal trigger (software) or event driven trigger (generated by external events). All trigger sources can work in tandem.
● An event driven trigger can be generated by external events on the Timing Connector’s External Event lines. Event and Mask registers are used to determine both the triggering event and the bits to be ignored or masked. These functions use the D Event and D Mask registers and the T Event and T Mask registers.
● External triggering can be initiated on sequential or concurrent events by using both D and T event registers to define events.
● Multiple pause sources are available: Programmed PXI Trigger line, External Pause, Internal pause (software) or event driven pause (generated by external events). All pause sources can work in tandem.
● The test sequence (vector) can be paused on external events unconditionally or conditionally. The P Event and P Mask registers define the condition and bits that generate a conditional pause.
● An X Register is used to emulate an External Event condition under program control for purposes of test program verification. The register is loaded through the computer bus.
● A DIO domain can be setup to use an internal or external clock, in order to synchronize with the user UUT.
● The DIO domain clock source (internal or external), when active, can be programmatically delayed by 0-27 nSec (increments of 0.25 nSec).
● DIO domain Strobe source (internal or external) which clocks input data can be programmatically delayed by 0-27 nSec (increments of 0.25 nSec).
● All GX5290/GX5290e Firmware can be upgraded through the DIO’s In-System- Programming (ISP) facility.
● Channel direction can be programmed on a per pin and per step basis at test rates up to 200MHz (GX5293/GX5293e).
● Programmable voltage levels (applied for all 32 channels) are supported for TTL logic families. via the TTL interface connector.
● Dual Data I/O interface connectors are provided, supporting LVDS (GX5292/GX5292e and GX5293) and TTL logic families (3.3V, 2.5V, 1.8V or 1.5V). TTL logic is only supported by the GX5291.
● User programmable PXI Star Trigger input supports Trigger and/or Pause functionality.
● The GX5290/GX5290e sequencer can halt or pause on a defined address, loop through the entire memory, or loop on a defined address or defined block of memory.
● All on-board memories are cleared (set low) whenever recycling power.
GX5292 Complete View
GX5292e Complete View