The GX5290/GX5290e Series are high performance, cost-effective 3U PXI dynamic digital I/O boards with 32 TTL I/O channels and 32 LVDS I/O (GX5292/GX5292e and GX5293) channels with dynamic direction control. The GX5290/GX5290e Series offers an industry leading 256MB (128MB for the Gx5291) of on-board memory and supports test rates up to 200 MHz (GX5293/GX5293e only). The single board design supports both master and slave functionality without the use of add-on modules. Output channel data is present on both LVDS (GX5292/GX5292e and GX5293) and TTL Standard level I/O connectors. If a channel is configured for input mode, the user can select (via software) which input interface to activate (GX5292/GX5292e and GX5293), i.e. LVDS or TTL level ( 3.3. 1.8, 1.5, or 2.5 volt logic levels). The GX5290 Series utilizes the PXI Local Bus to distribute signals across a domain. The GX5290e Series utilize the PXI backplane Trigger Bus lines to distribute signals across a domain (user defined).
The GX5292/GX5292e and GX5293 support deep pattern memory by offering 256 MB with 64 Mb per channel of on-board vector memory with dynamic per pin per step direction control and with test rates up to 200 MHz (GX5293 only). Separate memories are provided for output data, response data (input) and direction control. Each has 256 MB with 64 Mb per channel. The separate response data memory supports the recording of activity on the UUT pins independent of the bi-direction control.. Additionally, the GX5290 cards can be configured to support real-time digital compare, eliminating the need to capture and analyze acquired data.
The GX5291 offers 128 MB of memory, providing 32 Mb per channel of on-board vector memory with dynamic per pin per step direction control and with test rates up to 100 MHz. Separate memories are provided for output data, response data (input) and direction control. However, the GX5291 supports only TTL logic families and cannot operate with multiple cards (no master / slave support).
The GX5290/GX5290e provides programmable TTL/LVTTL output clocks and strobes, and supports external clock and strobe. A programmable PLL (phase locked loop) provides configurable clock frequencies and delays. An LVDS output clock is also provided. The GX5292/GX5292e’s sequencer can halt or pause on a defined address or loop through the entire memory as well as loop on a defined address range or through a defined block of memory.
The I/O stage can be software-configured to interface with a broad set of common TTL logic families including 5.0 V, 3.3 V, 2.5 V and 1.8 V families. In addition, a dedicated LVDS I/O interface is available via a dedicated connector (GX5292/GX5292e and GX5293). The I/O voltage stage can also be programmed with 10 mV resolution ranges from 1.4V to 3.6V which determines the logic high level for channels programmed to an output mode as well as defining the threshold level for channels configured as inputs.
The GX5290/GX5290e works as a complex programmable state machine with three main states: HALT, PAUSE and RUN. The central module of the board is the Vector Program Control. The Vector Program Control interprets predefined commands, controls the state machine and monitors the complex Trigger/Pause mechanism.
External control provides CLK, strobe and I/O pin direction from an external source. The combination of the external bi-directional control and external clocking, strobing, and triggering provides the capability to fully synchronize with UUTs and to minimize initialization procedures. The board sequencer permits looping over a predefined range of steps continuously or for a specific number of times. This provides the capability to generate stimulus vectors continuously at a defined test rate or for a pre-defined period of time.
Architecture Diagram