The clock (CLK) signal initiates each output vector. The rate of this signal can be programmed from 1Hz to 100MHz. Similarly, the strobe signal latches the input vector. All clock and strobe signals are distributed to all DIOs.
The GX5290’s clock architecture provides the user with the flexibility to align signals between the DIO and the Unit Under Test (UUT) using delay settings. The figure below is a block diagram of the clock architecture which includes programmable delays for the DIO clock and strobe. The clock signal is used to output test vectors, and strobe (clock) data into the DIO’s record memory. The basic architecture of the clock delay generator provides seven coarse delays in 4 ns steps. In addition a fine resolution delay (vernier) is available which provides a 0ns to 3ns delay in 250ps steps. Together, these elements provide delays in the range of 0ns to 27ns, with 250ps resolution for the data out and data input clocks.
Two clock signals are available for clocking input and output data:
O Clock |
The DIO sends output patterns to the I/O connector on the rising edge of the Clock (OCLK) signal. The Clock can have a delay of 0-27 nSec (with increments of 250 pSec) relative to the Out clock source. |
Out Clock |
This clock signal has the same source and frequency as the Clock without time delay. This is only an internal signal. |
Strobe |
The DIO captures input patterns from the I/O connector on the rising edge of Strobe (STB). When the Strobe source signal is internal, it has the same frequency as the Clock signal. The Strobe Clock can have a delay of 0-27 nSec (with increments of 250 pSec) relative to the Out clock source. The timing diagram in the figure below displays Out CLK and Strobe signals. The DIO board can be driven using either internal or external clock sources. In internal mode, Strobe occurs Ts nanoseconds before the next clock (CLK) signal (8 nSec default). Ts can be set from 0 – 24 nanoseconds before the Out CLK signal. In the external mode, Clock or Strobe signals are provided externally. |
A timing diagram of the CLK and Strobe signals is shown in the figure below:
Signal Timing Diagram