.gif "I/O Channel Block Diagram (J2 not used by the Gx5291)")
The operation of a GX5290/GX5290e board is best understood by studying the operation of a single I/O channel. Each of the 32 channels can be set independently to be either an input or output per step.
The figure below displays a simplified block diagram of a single I/O channel. This diagram shows how one channel functions.
I/O Channel Block Diagram (J2 not used by the Gx5291)
The Channel’s Direction control memory which is specified by the memory step is set to an output, enabling the Out Buffer and disabling the In Buffer. At the Out Buffer output there is an Output Enable Driver that is controlled by software. The output signal is then fed into two buffers: the Programmable Voltage Level Buffer and the LVDS Buffer (GX5292/GX5292e and GX5293). Both buffers will output the signals to the J1 and J2 connectors. The out signal that goes through the Programmable Voltage Level Buffer can have its Output logic high voltage level programmed using software (see specification for details). Data will be latched to both J1 and J2 connectors (GX5292/GX5292e and GX5293/GX5293e) on every rising Clock (when in RUN mode).
The Channel’s Direction control, which is specified by the memory step is set to an input, enabling the In Buffer and disabling the Out Buffer. The In Buffer input signal source can be programmed receive data from the J1 or J2 input. If selecting the Programmable Voltage Level Buffer, the threshold can be programmed using software (see Specifications for details). Data will be latched into memory on every rising Strobe clock edge (when the DIO is in RUN mode).