Architecture and Features

The following are key characteristics and features of the GX5295’s architecture:

     The GX5295 is a Plug and Play (PnP) board. The operating system (Windows 32/64-bit) automatically identifies and arbitrates resource requirements, notifies the user that a new board has been found and automatically installs the driver for it.

     A DIO domain operates independently of the host computer when in RUN mode.

     Each GX5295 DIO board supports a maximum clock frequency of up to 100MHz per channel for all channels.

     A GX5295 (Master) board controls the timing of its domain and can be synchronized to a UUT.

     Any GX5295 board can be configured programmatically to be a Master or Slave.

     Multiple Master boards are used to synchronize mutually asynchronous UUT elements.

     • Each GX5295 Slave board adds 32 UUT channels. Up to 15 Slave boards can be added to make a 512-channel domain.

     Each channel can be enabled or disabled on a per vector basis. Disabled output channels will be in a tri-state mode – facilitating the testing or emulation of bi-directional busses.

     Each Master has an external event bus. This bus is used for triggering and synchronizing with external events.

     4 auxiliary channels are available for use as input/ output triggers of events. These channels have programmable drive hi / drive lo and sense hi/ sense lo levels – identical to the features associated with the 32 I/O channels. Additionally, these channels have PMUs, providing additional parallel PMU test capability beyond the 32 I/O channels.

     Multiple trigger sources are available: Programmed PXI Trigger line, Star Trigger, External Trigger, Internal trigger (software) or event driven trigger (generated by external events). All trigger sources can work in tandem.

     An event driven trigger can be generated by external events on the Timing Connector’s External Event lines. Event and Mask registers are used to determine both the triggering event and the bits to be ignored or masked.  These functions use the D Event and D Mask registers and the T Event and T Mask registers.

     External triggering can be initiated on sequential or concurrent events by using both D and T event registers to define events.

     Multiple pause sources are available: Programmed PXI Trigger line, External Pause, Internal pause (software) or event driven pause (generated by external events). All pause sources can work in tandem.

     The test sequence (vector) can be paused on external events unconditionally or conditionally. The P Event and P Mask registers define the condition and bits that generate a conditional pause.

     An X Register is used to emulate an External Event condition under program control for purposes of test program verification. The register is loaded through the computer bus.

     A DIO domain can be setup to use an internal or external clock, in order to synchronize with the user UUT.

     The DIO domain clock source (internal or external), when active, can be programmatically delayed by 0-27 nSec (increments of 0.25 nSec) relative to the output data.

     DIO domain Strobe source (internal or external) which clocks input data  can be programmatically delayed by 0-27 nSec (increments of 0.25 nSec) relative to input data.

     All GX5295 Firmware can be upgraded through the DIO’s In-System- Programming (ISP) facility.

     Channel direction can be programmed on a per pin and per step basis at test rates up to 100MHz.

     User programmable PXI Star Trigger input supports Trigger and/or Pause functionality.

     The GX5295 sequencer can halt or pause on a defined address, loop through the entire memory, or loop on a defined address or defined block of memory.

     All on-board memories are cleared (set low) whenever recycling power.

     • Each channel has a full featured, pin electronics (PE) interface providing programmable drive high, drive low, sense, sense low, and active source and sink current load, and commutation voltage features. The drive / sense voltage range is -2 to +7 volts with a maximum swing of 8 volts p-p.

     Each channel also features a fully integrated Parametric Measurement Unit (PMU) for measuring a component’s DC characteristics. Each PMU operates independently and can be configured for force voltage / measure current or force current / measure voltage mode. 8 current force / measure ranges are supported, ranging from 32 mA to 2 uA full scale. The PMU voltage range is -2.0V to +7.0V volts. For high speed measurements, each PMU features programmable high / low limit comparators, allowing for the implementation of fast go / no-go PMU measurements.

Caution

Caution - Do not connect a device under test (DUT) to the GX5295’s I/O connections prior to powering up the card. Transient voltages can be present on the card’s I/O connectors at power up which can damage the DUT. Always disconnect the DUT prior to powering up the card.

 

The figure below shows a complete view of the GX5295 board. The GX5295 features two interface connectors, one for the 32 digital I/O channels and the other connector providing access to timing and event signals as well the four auxiliary PE channels.

View of a GX5295 board

The GX5295 board

The GX5295 board

Models and Accessories

The following GX5295 accessories are available:

     GT95014 – Connector interface, SCSI to 100 Mil Grid, Single Ended I/F Board

     GT95015 – Connector interface, SCSI to 100 Mil Grid, Differential I/F Board

     GT95021 – 2’ shielded cable (68-pin SCSI)

     GT95022 – 3’ Shielded cable (68-pin SCSI)

     GT95028 – 10’ Shielded cable (68-pin SCSI)

     GT95031 - 6’ Shielded cable (68-pin SCSI)