The memory subsystem is connected via the FPGA to the PXI bus and supports fast download or upload of vectors between the host computer and the GX5295.
Memory Management Block Diagram
The Clock/Strobe signals and the Vector Program Control hardware control the program counter that contains the address of the current I/O memory. After resetting, the program counter points to address zero which is then incremented by the Clock/Strobe signal as the program is sequenced by the Vector Program Control hardware.