Output Data Block Diagram
The above figure is a block diagram of a single pin when operating in output mode. Up to 16 boards can be used in one domain for a maximum of 512 pins (each board containing 32 I/O pins). Output data, which is stored in the output memory, is outputted from the board as a function of the Out Clock signal through the pin electronics and the direction memory. The data will be latched to the output pin if the Direction Memory at that location was set to output. The direction memory enables the pin electronics output when the specified step is defined as an output step. The output data to the UUT will also be stored in the input memory via the receiver pin electronics.
Each data channel’s output signal has programmable drive high and drive low levels. The drive high level can be set from -2.0 volts to +7.0 volts and must be greater than the output driver’s drive low voltage. The output driver’s drive low voltage can be set from -2.0 volt to +7.0 volts. Total swing is limited to 8 volts.
Each output driver has over current protection that limits the maximum current that can be sourced from any channel (The channel can sustain a short circuit condition. Once the short circuit condition is removed, the channel resumes normal operation).
In order to align propagation delay between channels each channel’s driver data and driver output enable has a programmable skew delay. Skew delay can be programmed separately for the rising and falling edges or for only the falling edge. Output Skew delay can be set from 0 ns to + 4.6875 ns with 19.53 ps of resolution. Output falling edge skew delay can be set from -2.5 ns to +2.1875 ns with 19.53 ps of resolution. The falling edge delay circuitry adds or subtracts timing delay to or from the falling edge while having no effect on the rising edge. Propagation delay adjustment is typically used for removing any pulse width distortion inside a tester. The propagation delay circuitry adds timing delay to the rising edge and the falling edge in equal amounts. Propagation delay adjustment is typically used for aligning the timing of multiple channels inside a tester. The output data skew delay adds delay to the output driver data in reference to the DIO clock. While the output enable data skew delay adds delay to the output driver data enable in reference to the DIO clock. Delaying the output data enable adds an additional delay to the output driver’s data in reference to the DIO clock. Each channel’s output has the following timing features:
● Separate and independent delay circuitry for the driver output data and the driver output data enable.
● Separate and independent delay circuitry for each channel.
● Programmable propagation delay adjusts both rising and falling edge equally.
● Programmable falling edge delay circuitry adds or subtracts timing delay to or from the falling edge while having no effect on the rising edge.
Note: Approximately 2 ns of skew delay is reserved for deskewing the GX5295’s output channels, leaving approximately 2.5 ns available for user applications.