GT5920 Frequency Doubler I/O Module

The GT5920 100MHz frequency multiplier module increases the upper test rate limit to 100MHz. The increase in test rate is achieved by interleaving a single I/O pin into two parallel memory locations. The GT5920 provides 16 Input or Output pins (in groups of 8 pins). The GT5920 is a GT5150 and GT5900 plug-in unit.

A picture of the GT5920 is displayed in the figure below:

GT5920 Frequency Doubler Module

Architecture

The GT5920 frequency multiplier module converts the 32, 50MHz I/O channels into 16, 100MHz I/O channels. The memory MUX/interleave logic is designed into a single high-speed programmable logic device, thereby minimizing propagation delays. Concurrent high and low word memory locations are interleaved using opposite phases of the programmable output clock. Each I/O pin has a corresponding termination that can be globally enabled or disabled through software control.

Programming

The GT5920 Module is controlled via the host GT5150 or GT5900. Programmable functions include:

●     Signal termination enable/disable

●     I/O data direction (not dynamic)

●     Tri-state control

Block Diagram

A block diagram of the GT5920 is displayed in the figure below:

GT5920 Block Diagram

Function

The GT5920 I/O Module doubles the data rate between GT515X or GT50-DIO main boards and TTL-level UUTs. The maximum data rate doubles and can switch up to 120 MHz. Clock rate is doubled with a phase-locked loop, which has an input range of 10 60MHz. The output range is 20 120 MHz.

This module mounts as a daughter card directly on a GT515X main board or a GT5900 ISA Carrier. Although a GT25-DIO can also benefit from this I/O module, its speed can be improved more efficiently by upgrading it to a GT50-DIO.

Data rate doubling is achieved by interleaving DIO data channel pairs. Data is multiplexed on opposite clock phases. The number of active channels is consequently halved (16 of 32 or 8 of 16 for a GT515X using width control). There is a latency delay of three input clocks that must be accounted for in the testware program.

Control

Direction Control - Static I/O direction switching. Configured when set up.

Byte Control - Dynamic output enable/disable for GT515X boards under vector control.

Width Control Supports eight or sixteen bit widths for GT515X memory depth enhancement.

Termination Line terminators can be switched in or out under program control. 180/330 W or 330/390 W SIPs are standard. SIPs mount in sockets to accept other (user-supplied) termination values.

UUT-Side I/O Data

The table below describes GT5150 (J4)/GT5900 (J10 or J11) to UUT data signals when a GT5920 I/O Module is mounted on the motherboard.

                                Legend:                 

                   UUT-Side I/O Connections with a GT5920 Mounted

I/O pin data rates are clocked at the XClk and OClk frequency, which is double the rate of XClk and OClk on the Masters Timing module. A low on ClkSel forces the use of XClk.

The table UUT-Side I/O Connections with a GT5910 Mounted describes GT515X signals at J4 and Carrier signals at J11. It also describes Carrier signals at J10 when the Carrier is used only for I/O data.

Specifications