Counter outputs A4 and A5 are initially in an unknown state and are mapped to DIO channels 8 and 9. They also connect to the two LSBs on the DIO External Event input bus. (Other External Event bus inputs are grounded). DIO channel 0 (CLK) generates the board clock input. There is no way to reset the counter. When initializing the board to a known state, the counter is clocked and its output sampled until the desired starting count, A4 and A5 both low, is present.
The table below displays a GC5050/GX5050 board setup to initialize the counter. The table specifies channels, channel groups, channel names and direction along with commands, labels and values for the first 20 steps. It is followed by a detailed explanation.
|
I/O Ch |
0 |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
16 |
17 |
18 |
19 |
||||||||||
|
Ch. Group Direction |
|
Group |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
2 |
2 |
3 |
3 |
3 |
3 |
||||||||
Step |
Label |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
Cmd |
Op/ |
CLK |
CLR |
RD |
WR |
AO |
A1 |
A2 |
A3 |
A4 |
A5 |
D0 |
D1 |
D2 |
D3 |
0 |
CNTINIT |
0 |
I |
0 |
|
|
|
|
|
|
|
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
X |
X |
X |
X |
X |
X |
1 |
|
0 |
I |
0 |
|
|
|
|
|
|
|
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
X |
X |
X |
X |
X |
X |
2 |
|
0 |
I |
0 |
|
|
|
|
|
|
|
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
X |
X |
X |
X |
X |
X |
3 |
|
0 |
I |
0 |
|
|
|
|
|
Set A |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
X |
X |
X |
X |
X |
X |
4 |
|
0 |
I |
0 |
|
|
|
|
|
|
|
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
X |
X |
X |
X |
X |
X |
5 |
|
0 |
I |
0 |
|
|
|
|
|
|
|
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
X |
X |
X |
X |
X |
X |
6 |
|
0 |
I |
0 |
|
|
|
|
|
|
|
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
X |
X |
X |
X |
X |
X |
7 |
|
0 |
I |
0 |
|
|
|
|
|
Set B |
4 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
X |
X |
X |
X |
X |
X |
8 |
LOOPINIT |
0 |
I |
0 |
|
|
|
|
|
|
|
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
X |
X |
X |
X |
X |
X |
9 |
|
0 |
I |
0 |
|
|
|
|
|
|
|
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
X |
X |
X |
X |
X |
X |
10 |
|
0 |
I |
0 |
|
|
|
|
|
|
|
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
X |
X |
X |
X |
X |
X |
11 |
|
0 |
I |
0 |
|
|
|
|
|
JE A |
RAMTEST |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
X |
X |
X |
X |
X |
X |
12 |
|
0 |
I |
0 |
|
|
|
|
|
|
|
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
X |
X |
X |
X |
X |
X |
13 |
|
0 |
I |
0 |
|
|
|
|
|
|
|
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
X |
X |
X |
X |
X |
X |
14 |
|
0 |
I |
0 |
|
|
|
|
|
|
|
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
X |
X |
X |
X |
X |
X |
15 |
|
0 |
I |
0 |
|
|
|
|
|
LOOP B |
LOOPINIT |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
X |
X |
X |
X |
X |
X |
16 |
|
0 |
I |
0 |
|
|
|
|
|
|
|
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
X |
X |
X |
X |
X |
X |
17 |
|
0 |
I |
0 |
|
|
|
|
|
|
|
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
X |
X |
X |
X |
X |
X |
18 |
|
0 |
I |
0 |
|
|
|
|
|
|
|
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
X |
X |
X |
X |
X |
X |
19 |
|
0 |
I |
0 |
|
|
|
|
|
HALT |
|
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
X |
X |
X |
X |
X |
X |
20 |
RAMTEST |
0 |
I |
0 |
|
|
|
|
|
|
|
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
X |
X |
X |
X |
X |
X |
Notes: O = Output, I = Input; X = Don’t care
The following steps explain the commands in the table above.
1. Set Register A to zero 0 (Step 3).
2. Set Register B to 4 (Step 7).
3. A conditional JUMP to the RAMINIT label occurs if EXT=A. This ensures that the program will terminate that loop (by jumping to Step 20) when the two LSB outputs of the Counter reach the “00” state (Step 11).
4. The CLK input goes low to provide the Counter with a clock signal (Step 12).
5. The CLK input returns to high (Step 14) and the sequencer performs an unconditional jump to LOOPINIT (Step 8).
6. Set a trap to HALT the program in the event the Counter cannot be initialized. Regardless of its initial state, the Counter should be initialized in 1 to 3 clock signals. The described LOOP will provide a maximum of 4 clock signals before entering the trap (Step 19).