Testing the D Flip-flop

The last test is designed to verify functionality of the D flip-flop. In Step 411 (the table below), CLR is applied to force the U/D input to logic high. CLK at Step 412 causes the Counter to count down to A4=0 and A5=1. The RD cycle in Step 414 will read address 0 from the 3rd bank (AA).

At Step 415, the sequencer “End Of Program” command ends the test.

The table below demonstrates a program for testing the D flip-flop.

 
I/O Ch
0
1
2
3
4
5
6
7
8
9
16
17
18
19
 
Ch. Group Direction
 
Group
1
1
1
1
1
1
1
1
2
2
3
3
3
3
Step
Label
1
2
3
4
5
6
7
8
Cmd
Op/
Label
CLK
CLR
RD
WR
AO
A1
A2
A3
A4
A5
D0
D1
D2
D3
411
 
0
I
I
 
 
 
 
 
 
 
1
0
1
1
1
1
1
1
1
1
X
X
X
X
412
 
0
I
I
 
 
 
 
 
 
 
0
0
1
1
1
1
1
1
1
1
X
X
X
X
413
 
0
I
I
 
 
 
 
 
 
 
1
0
1
1
0
0
0
0
0
1
X
X
X
X
414
RD0
0
I
I
 
 
 
 
 
 
 
1
0
0
1
0
0
0
0
0
1
1
0
1
0
415
END
0
I
I
 
 
 
 
 
HALT
 
1
0
1
1
0
0
0
0
0
1
X
X
X
X

Testing the D Flip-flop