Testing the RAM

Writing to the RAM

When the test program reaches Step 20, the counter outputs A4 and A5 are both low and the UUT is initialized. Now Group 2 channels (including channels 8 - 9) are redefined as receivers with well-defined inputs.

At Step 20, Group 3 (D0, D3, including channels 16-19) is now reversed and outputs 0000 (0x0) to the board. LSB Address lines A0 - A3 are set to 0x0.

At Step 21 (table below), WR is driven low at Channel 3 to enable writing to RAM. In Step 22, WR is returned high. Three steps are used for each WR cycle: (1) to avoid “races” within the UUT, (2) to assure that data and address inputs are stable when the WR signal is applied, and (3) to assure that data and address inputs are static while WR is active.

These three steps repeat 64 times. Data is written to all memory locations. For the first 16 locations, data written to RAM is set to the address on lines A0-A3. In the second 16, it is inverted. In the third 16, 0xAA is written and in the final 16 locations, 0x55 is written.

After the first 16 write cycles, channel 0 is clocked to increment the counter to state 01 while writing continues for the next 16 cycles, etc. Step 214 completes writing to RAM.

The table below describes DIO channels and steps that have been implemented to write data to RAM.

     Writing to RAM

Reading from RAM

To complete the test, all RAM locations are read back. In Step 215, the direction of Group 3 (channels 16-19) is changed to input. The expected data is defined only when the RD signal is set low.

After reading the first 16 locations, the Counter advances to the position (Step 264) to initiate an additional cycle to read the next 16 locations, etc.

The table below describes DIO channels and steps for reading the RAM. The result of this reading can then be compared to the data actually written to RAM.

Reading from RAM