The DAC’s linear range is a ±10.0 volt. Our objective is to generate either of two waveforms in accordance with the LBC waveform line (Wvfm), a continuos saw or a triangular wave between 0 and 5 V.
The DAC is initialized before the main test program starts. A Master Clear (MC) signal resets the DAC and the LBC.
When the system wants the DAC to generate a waveform, it issues an address that is interpreted by the LBC as a request for the indicated value. When the DIO is ARMed, after initializing the DAC and LBC, the BusReq is set to low and the DIO is now in PAUSE state. The LBC has control of the bus; it responds by lowering the BusAv line which triggers the DIO. The DIO then changes to the RUN state. While in RUN state the 8-bits of data are enabled. At that point the OutEn line will be set to low, signaling to the LBC that the data bus is now occupied by the DIO. That line will stay low as long as the DIO is in the RUN state.
When the Wvfm is low then a saw waveform is selected. The DIO will produce a series of steps starting from 0 to 127, after each new value a Clk is issued to strobe the voltage level into the DAC’s input register. Waveforms will be output continuously until a Stop signal is received from the UUT.
When the Wvfm is high then a triangle waveform is selected. The DIO starts to output a sequence of values stating from 0 V to 5 V and back to 0 V. For each waveform value the DIO issues a Clk to strobe the new value into the DAC’s input register. Waveforms will be output continuously until a Stop signal is received from the UUT.
Waveform selection can be change dynamically by setting the waveform line to either low or high at any point.
The UUT can stop the DIO by setting the Stop to low. The DIO immediately will be set to the HALT state.