P8 and P9 Host Connectors

The following table describes the GX3500 expansion board P8 and P9 pin assignments:

Pin #
Name
Function
FPGA Pin #
Notes
Pin #
Name
Function
FPGA Pin #
Notes
1
+12V
Power
 
1
2
-12V
Power
 
1
3
NC
Not Connected
 
 
4
NC
Not Connected
 
 
5
PSpr0
Do Not Use
 
2
6
NC
Not Connected
 
 
7
PSpr1
Do Not Use
 
2
8
NC
Not Connected
 
 
9
PSpr2
Do Not Use
 
2
10
NC
Not Connected
 
 
11
PSpr3
Do Not Use
 
2
12
NC
Not Connected
 
 
13
NC
Not Connected
 
 
14
NC
Not Connected
 
 
15
NC
Not Connected
 
 
16
FSpr0
Out, Spare
G9
4,6
17
NC
Not Connected
 
 
18
FSpr1
Out, Spare
F7
4,6
19
PbID0
Out, Piggy Back ID
 
3
20
FSpr2
Out, Spare
F9
4,6
21
PbID1
Out, Piggy Back ID
 
3
22
FSpr3
Out, Spare
G7
4,6
23
PbID2
Out, Piggy Back ID
 
3
24
NC
Not Connected
 
 
25
PbID3
Out, Piggy Back ID
 
3
26
MClr
In, Master Clear
 
5
27
NC
Not Connected
 
 
28
NC
Not Connected
 
 
29
FlexIO120
3.3V LVTTL IO
G8
6, 7
30
FlexIO41
3.3V LVTTL IO
F14
6, 7
31
FlexIO119
3.3V LVTTL IO
F8
6, 7
32
FlexIO42
3.3V LVTTL IO
G11
6, 7
33
FlexIO118
3.3V LVTTL IO
F10
6, 7
34
FlexIO43
3.3V LVTTL IO
G14
6, 7
35
FlexIO117
3.3V LVTTL IO
G10
6, 7
36
FlexIO44
3.3V LVTTL IO
F13
6, 7
37
FlexIO116
3.3V LVTTL IO
G13
6, 7
38
FlexIO45
3.3V LVTTL IO
G16
6, 7
39
FlexIO115
3.3V LVTTL IO
F11
6, 7
40
FlexIO46
3.3V LVTTL IO
G15
6, 7
41
FlexIO114
3.3V LVTTL IO
H16
6, 7
42
FlexIO47
3.3V LVTTL IO
L6
6, 7
43
FlexIO113
3.3V LVTTL IO
H17
6, 7
44
FlexIO48
3.3V LVTTL IO
J17
6, 7
45
FlexIO112
3.3V LVTTL IO
N17
6, 7
46
FlexIO49
3.3V LVTTL IO
M6
6, 7
47
FlexIO111
3.3V LVTTL IO
M16
6, 7
48
FlexIO50
3.3V LVTTL IO
W20
6, 7
49
FlexIO110
3.3V LVTTL IO
R18
6, 7
50
FlexIO51
3.3V LVTTL IO
N7
6, 7
51
FlexIO109
3.3V LVTTL IO
N16
6, 7
52
FlexIO52
3.3V LVTTL IO
U19
6, 7
53
FlexIO108
3.3V LVTTL IO
P20
6, 7
54
FlexIO53
3.3V LVTTL IO
P7
6, 7
55
FlexIO107
3.3V LVTTL IO
P17
6, 7
56
FlexIO54
3.3V LVTTL IO
W19
6, 7
57
FlexIO106
3.3V LVTTL IO
R17
6, 7
58
FlexIO55
3.3V LVTTL IO
M5
6, 7
59
FlexIO105
3.3V LVTTL IO
R19
6, 7
60
FlexIO56
3.3V LVTTL IO
T18
6, 7
61
FlexIO104
3.3V LVTTL IO
R20
6, 7
62
FlexIO57
3.3V LVTTL IO
Y17
6, 7
63
FlexIO103
3.3V LVTTL IO
T19
6, 7
64
FlexIO58
3.3V LVTTL IO
W17
6, 7
65
FlexIO102
3.3V LVTTL IO
T17
6, 7
66
FlexIO59
3.3V LVTTL IO
U17
6, 7
67
FlexIO101
3.3V LVTTL IO
T20
6, 7
68
FlexIO60
3.3V LVTTL IO
U16
6, 7
69
FlexIO100
3.3V LVTTL IO
N6
6, 7
70
FlexIO61
3.3V LVTTL IO
U15
6, 7
71
FlexIO99
3.3V LVTTL IO
U20
6, 7
72
FlexIO62
3.3V LVTTL IO
Y15
6, 7
73
FlexIO98
3.3V LVTTL IO
P6
6, 7
74
FlexIO63
3.3V LVTTL IO
W15
6, 7
75
FlexIO97
3.3V LVTTL IO
N18
6, 7
76
FlexIO64
3.3V LVTTL IO
V16
6, 7
77
FlexIO96
3.3V LVTTL IO
N19
6, 7
78
FlexIO65
3.3V LVTTL IO
V15
6, 7
79
FlexIO95
3.3V LVTTL IO
N20
6, 7
80
FlexIO66
3.3V LVTTL IO
Y14
6, 7
81
FlexIO94
3.3V LVTTL IO
J21
6, 7
82
FlexIO67
3.3V LVTTL IO
W14
6, 7
83
FlexIO93
3.3V LVTTL IO
K21
6, 7
84
FlexIO68
3.3V LVTTL IO
V14
6, 7
85
FlexIO92
3.3V LVTTL IO
L21
6, 7
86
FlexIO69
3.3V LVTTL IO
U14
6, 7
87
FlexIO91
3.3V LVTTL IO
M22
6, 7
88
FlexIO70
3.3V LVTTL IO
Y13
6, 7
89
FlexIO90
3.3V LVTTL IO
M21
6, 7
90
FlexIO71
3.3V LVTTL IO
W13
6, 7
91
FlexIO89
3.3V LVTTL IO
N22
6, 7
92
FlexIO72
3.3V LVTTL IO
V13
6, 7
93
FlexIO88
3.3V LVTTL IO
P22
6, 7
94
FlexIO73
3.3V LVTTL IO
U13
6, 7
95
FlexIO87
3.3V LVTTL IO
P21
6, 7
96
FlexIO74
3.3V LVTTL IO
V12
6, 7
97
FlexIO86
3.3V LVTTL IO
R22
6, 7
98
FlexIO75
3.3V LVTTL IO
U12
6, 7
99
FlexIO85
3.3V LVTTL IO
R21
6, 7
100
FlexIO76
3.3V LVTTL IO
V11
6, 7
101
FlexIO84
3.3V LVTTL IO
U22
6, 7
102
FlexIO77
3.3V LVTTL IO
U11
6, 7
103
FlexIO83
3.3V LVTTL IO
U21
6, 7
104
FlexIO78
3.3V LVTTL IO
Y10
6, 7
105
FlexIO82
3.3V LVTTL IO
V22
6, 7
106
FlexIO79
3.3V LVTTL IO
W10
6, 7
107
FlexIO81
3.3V LVTTL IO
V21
 
6, 7
108
FlexIO80
3.3V LVTTL IO
V10
6, 7
109
NC
Not Connected
 
6, 7
110
NC
Not Connected
 
 
111
1.2V
Power
 
8
112
2.5V
Power
 
9
113
1.2V
Power
 
8
114
2.5V
Power
 
9
115
1.2V
Power
 
8
116
2.5V
Power
 
9
117
1.2V
Power
 
8
118
2.5V
Power
 
9
119
1.2V
Power
 
8
120
2.5V
Power
 
9
A
GND
Power
 
 
B
GND
Power
 
 
C
GND
Power
 
 
D
GND
Power
 
 
E
GND
Power
 
 
F
GND
Power
 
 
G
GND
Power
 
 
H
GND
Power
 
 
J
GND
Power
 
 
K
GND
Power
 
 
L
GND
Power
 
 
M
GND
Power
 
 

P8 Connector pin assignments

 

The following table describes the GX3500 expansion board P9 pin assignments:

Pin #
Name
Function
FPGA Pin #
Notes
Pin #
Name
Function
FPGA Pin #
Notes

1
FlexIO160
3.3V LVTTL IO
Y22
6,7
2
-12V
3.3V LVTTL IO
W22
6, 7

3
FlexIO159
3.3V LVTTL IO
Y21
6,7
4
NC
3.3V LVTTL IO
W21
6, 7

5
FlexIO158
3.3V LVTTL IO
AA22
6,7
6
NC
3.3V LVTTL IO
V9
6, 7

7
FlexIO157
3.3V LVTTL IO
AA21
6,7
8
NC
3.3V LVTTL IO
V8
6, 7

9
FlexIO156
3.3V LVTTL IO
AB20
6,7
10
NC
3.3V LVTTL IO
W8
6, 7

11
FlexIO155
3.3V LVTTL IO
AA20
6,7
12
NC
3.3V LVTTL IO
Y8
6, 7

13
FlexIO154
3.3V LVTTL IO
AB19
6,7
14
NC
3.3V LVTTL IO
V7
6, 7

15
FlexIO153
3.3V LVTTL IO
AA19
6,7
16
FSpr0
3.3V LVTTL IO
W7
6, 7

17
FlexIO152
3.3V LVTTL IO
AB18
6,7
18
FSpr1
3.3V LVTTL IO
Y7
6, 7

19
FlexIO151
3.3V LVTTL IO
AA18
6,7
20
FSpr2
3.3V LVTTL IO
V6
6, 7

21
FlexIO150
3.3V LVTTL IO
AB17
6,7
22
FSpr3
3.3V LVTTL IO
W6
6, 7

23
FlexIO149
3.3V LVTTL IO
AA17
6,7
24
NC
3.3V LVTTL IO
Y6
6, 7

25
FlexIO148
3.3V LVTTL IO
AB16
6,7
26
MClr
3.3V LVTTL IO
V5
6, 7

27
FlexIO147
3.3V LVTTL IO
AA16
6,7
28
NC
3.3V LVTTL IO
Y4
6, 7

29
FlexIO146
3.3V LVTTL IO
AB15
6, 7
30
FlexIO41
3.3V LVTTL IO
Y3
6, 7

31
FlexIO145
3.3V LVTTL IO
AA15
6, 7
32
FlexIO42
3.3V LVTTL IO
V4
6, 7
33
FlexIO144
3.3V LVTTL IO
AB14
6, 7
34
FlexIO43
3.3V LVTTL IO
V3
6, 7
35
FlexIO143
3.3V LVTTL IO
AA14
6, 7
36
FlexIO44
3.3V LVTTL IO
U2
6, 7
37
FlexIO142
3.3V LVTTL IO
AB13
6, 7
38
FlexIO45
3.3V LVTTL IO
U1
6, 7
39
FlexIO141
3.3V LVTTL IO
AA13
6, 7
40
FlexIO46
3.3V LVTTL IO
T3
6, 7
41
FlexIO140
3.3V LVTTL IO
AA10
6, 7
42
FlexIO47
3.3V LVTTL IO
T4
6, 7
43
FlexIO139
3.3V LVTTL IO
AB10
6, 7
44
FlexIO48
3.3V LVTTL IO
T5
6, 7
45
FlexIO138
3.3V LVTTL IO
AA9
6, 7
46
FlexIO49
3.3V LVTTL IO
R4
6, 7
47
FlexIO137
3.3V LVTTL IO
AB9
6, 7
48
FlexIO50
3.3V LVTTL IO
R3
6, 7
49
FlexIO136
3.3V LVTTL IO
AA8
6, 7
50
FlexIO51
3.3V LVTTL IO
R2
6, 7
51
FlexIO135
3.3V LVTTL IO
AB8
6, 7
52
FlexIO52
3.3V LVTTL IO
R1
6, 7
53
FlexIO134
3.3V LVTTL IO
AA7
6, 7
54
FlexIO53
3.3V LVTTL IO
P4
6, 7
55
FlexIO133
3.3V LVTTL IO
AB7
6, 7
56
FlexIO54
3.3V LVTTL IO
P3
6, 7
57
FlexIO132
3.3V LVTTL IO
AA6
6, 7
58
FlexIO55
3.3V LVTTL IO
P2
6, 7
59
FlexIO131
3.3V LVTTL IO
AB6
6, 7
60
FlexIO56
3.3V LVTTL IO
P1
6, 7
61
FlexIO130
3.3V LVTTL IO
AA5
6, 7
62
FlexIO57
3.3V LVTTL IO
N2
6, 7
63
FlexIO129
3.3V LVTTL IO
AB5
6, 7
64
FlexIO58
3.3V LVTTL IO
N1
6, 7
65
FlexIO128
3.3V LVTTL IO
AA4
6, 7
66
FlexIO59
3.3V LVTTL IO
M4
6, 7
67
FlexIO127
3.3V LVTTL IO
AB4
6, 7
68
FlexIO60
3.3V LVTTL IO
M3
6, 7
69
FlexIO126
3.3V LVTTL IO
AA3
6, 7
70
FlexIO61
3.3V LVTTL IO
M2
6, 7
71
FlexIO125
3.3V LVTTL IO
AB3
6, 7
72
FlexIO62
3.3V LVTTL IO
M1
6, 7
73
FlexIO124
3.3V LVTTL IO
AA2
6, 7
74
FlexIO63
3.3V LVTTL IO
W2
6, 7
75
FlexIO123
3.3V LVTTL IO
AA1
6, 7
76
FlexIO64
3.3V LVTTL IO
W1
6, 7
77
FlexIO122
3.3V LVTTL IO
Y2
6, 7
78
FlexIO65
3.3V LVTTL IO
V2
6, 7
79
FlexIO121
3.3V LVTTL IO
Y1
6, 7
80
FlexIO66
3.3V LVTTL IO
V1
6, 7

A
3.3V
Power
 
10
B
GND
Power
 
 

C
3.3V
Power
 
10
D
GND
Power
 
 

E
3.3V
Power
 
10
F
GND
Power
 
 

G
3.3V
Power
 
10
H
GND
Power
 
 

P9 Connector pin assignments

Notes for Host connectors:

1.    Maximum 0.5A. May be limited by PXI chassis. Connect a 10uF-22uF capacitor if using these pins.

2.    PSpr[3..0] are reserved. Should be connected to ground using 1K-50K resistors.

3.    PbID[3..0] are used to identify the expansion board. Leave pins unconnected for logic ‘1’ or connect to ground for logic ‘0’. The GX3500 software driver can read these pins to identify the specific expansion board installed on the GX3500.

4.    FSpr[3..0] are spare pins connected to the user FPGA. Should be connected to ground or 3.3V using 1K-50K resistors if not used in the design. Can also be used as an additional identification field.

5.    MClr is a Master Clear input to the Expansion board. It is active low and is asserted by the controller at power-up or by a software command at any time.

6.    These signals must never drive more than 3.3V. If 5V logic is used in the Expansion board design, these pin must be protected.

7.    During the user FPGA configuration phase, these pins have a weak pull-up that may cause an un-intentional condition in the Expansion board design. Pull-down resistors should be used where necessary.

8.    Connect these pins together. Maximum 1A for the 1.2V rail. Connect a 10uF-22uF capacitor if using these pins.

9.    Connect these pins together. Maximum 0.5A for the 2.5V rail. Connect a 10uF-22uF capacitor if using these pins.

10.  Connect these pins together. Maximum 4A for the 3.3V rail. May be limited by PXI chassis. Connect a 10uF-22uF capacitor if using these pins.