This tutorial will go over the basic workflow to start designing and loading a FPGA configuration for the Gx3500. The contents will entail:
Downloading and installing the FPGA design tool.
Creating a new FPGA Design project with the Cyclone III as the target device.
Setup the pin assignment to work with the GX3500 and Cyclone III FPGA.
Use the graphical design tool to create an example FPGA configuration.
Compile the project and generate the SVF and RPD programming files.
Loading the board with the generated programming files.
Testing the design using the Gx3500 Front Panel software and ATEasy.
The example configuration is broken down into three phases, each with a distinct function:
Phase 1: Take two values located in PCI Registers and generate a Sum (Adder) which can then be read through a third PCI Register.
Phase 2: 2 to 1 multiplexer to choose between the 10 MHz Clock and the PCI Clock which will be output on one of the FlexIO pins. The clock will be selected through a PCI Register.
Phase 3: A simple dynamic digital sequencer with a memory depth of 32 double words (written to through the PCI bus) driven by a PLL that continuously outputs digital patterns to the first 32 FlexIO pins.
The source code for the examples in this chapter is provided in the Examples\Quartus folder.