The GX3500’s four banks of 40 digital I/O signals can be selectively isolated from the I/O connectors under software control. The signals are 5 volt tolerant and can be configured to support differential or single-ended operation. Logic families supported by the I/O interface include LVTTL and LVCMOS. The FPGA device supports up to four phase lock loops for clock synthesis, clock generation and for support of the I/ O interface. An on-board 80 MHz oscillator is available for use with the FGPA device or alternatively, the PXI 10 MHz clock can be used as a clock reference by the FPGA.
The FPGA has access to all of the PXI bus resources including the PXI 10 MHz clock, the local bus, and the PXI triggers, allowing the user to create a custom instrument which incorporates all of the PXIbus’ resources. Control and access to the FPGA is provided via the GX3500’s driver (GxFPGA) which includes tools for downloading the compiled FPGA code as well as providing register read and write functionality.
The GX3500 employs an Altera Cyclone III, 484 pin device. Key features for the Altera device include:
55,856 logic elements (LEs) and 2.34 Mbits of memory.
Supports up to four phase-locked loops (PLLs) for clock synthesis, clock generation and support of I/O interfaces.
Up to five outputs per PLL can be accessed.
Dynamically reconfigurable logic supports programmable phase shift, frequency multiplication/division, and in-system frequency re-programming without reconfiguring the device.
Support for high-speed external memory interfaces including DDR, DDR2, SDR , SDRAM, and QDRII SRAM at up to 400 megabits per second (Mbps).
327 I/O pins arranged in eight I/O banks that support a wide range of industry I/O standards.
Supports up to 875 Mbps receive and 840 Mbps transmit LVDS communications data rates.
Support for Bus LVDS (BLVDS), LVDS, RSDS®, mini-LVDS and PPDS® differential I/O standards.
Supported I/O standards include LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X, LVPECL, LVDS, mini-LVDS, RSDS, and PPDS; PCI Express Base.