Specifications

The following table outlines the specifications of the GX3500:

Digital I/O Channel

Logic Families
LVTTL and LVCMOS, 5 volt compatible.
Output Current
+/ 4.0 mA.
Input Leakage Current
+/- 10 uA.
Power On State
Programmable by line, default is disconnect at power on.
Number of Channels
4 banks of 40 I/O signals. Direction is configurable on a per pin basis Disconnect on a per bank basis.
Protection
Overvoltage: -0.5V to 7.0V (input) Short circuit: up to 8 outputs may be shorted at a time.
Connectors
(4) SCSI III, VHDCI type, 68 pin female.

 

Expansion Board Interface

Board ID

4 bits.

Digital I/O

160, each bank of 40 can be configured to bypass or access the expansion board.

FPGA Flex I/O

4 signals.

Master Clear

From PXI interface.

Power

+/- 12 volts, +5 volts, +3.3 volts, +2.5 volts, +1.2 volts.

 

Timing Source

PXI 10 MHZ

PXI Bus.

Internal

80 MHz oscillator, +/- 20 ppm.

 

User FPGA

FPGA Type

Cyclone III, EP3C55 F484.

Number of PLLs

Four.

Logic Elements

55,856.

Internal Memory

2.34 Mb.

 

Power

3.3 VDC

400 mA (typ.);  1 A (Max.)

5 VDC

300 mA (typ.);  1.2 A (Max.)

12 VDC (For Expansion Board)

 

 

Environmental

Operating Temperature

0 to 50° C.

Storage Temperature

-20° C to 70° C.

Size

3U PXI.

Weight

200 g.