Number
of Channels |
160
I/O; up to 84 I/O can be configured as 42 differential I/O channels
4 I/O
are single-ended or 2 differential clock inputs. |
Logic
Family |
LVTTL,
LVDS, configurable for 1.2 / 2.5 / 3.3 V logic; 5 V compatible;
user programmable via the FPGA.
|
Output
Current |
± 12 mA,
sink or source, max. Programmable via the FPGA. |
Input
Leakage Current |
± 10 uA.
|
Power
On State |
Default
is disconnected at power on (unprogrammed FPGA) or defined by
FPGA program. |
Input
Protection |
Overvoltage:
-0.5 V to 7.0 V (input).
Short
circuit: up to 8 outputs may be shorted at a time. |