This tutorial will go over the basic workflow to start designing and loading a FPGA configuration for the Gx3700. The example provides creation of a project using VHDL sources and coding. The “Tutorial design top reg.doc” contains the design register map.
The tutorial contents will entail:
Downloading and installing the FPGA design tool.
Creating a new FPGA Design project with the Stratix III as the target device.
Setup the pin assignment to work with the GX3700 and Stratix III FPGA.
Use the Quartus IDE to create an example FPGA configuration.
Compile the project and generate the SVF and RPD programming files.
Loading the board with the generated programming files.
Testing the design using the Gx3700 Front Panel software and ATEasy
The example configuration is broken down into two phases, each with a distinct function:
Phase 1: Take two values located in PCI Registers and generate a Sum (Adder) which can then be read through a third PCI Register.
Phase 2: 2 to 1 multiplexer to choose between the 10 MHz Clock and the PCI Clock which will be output on one of the FlexIO pins. The clock will be selected through a PCI Register. We will also create a clock divider to divide down the PCIClock (33MHz) and drive IRQ generation at ~4Hz.
The source code for the examples in this chapter is provided in the Examples\Quartus\Gx3700 folder.