This design will output either the PCI Clock (33Mhz) or the 10Mhz clock to FlexIO Channel 65 (Check connectors tables for the correct pin location) depending on what was written to the 4th double word in the PCI register space (byte offset 0xC). A 1 will select the 10Mhz clock signal, and a 0 will select the PCI clock signal.
You will now build upon the tutorial project to add the functionality of a 2 to 1 Clock Mux. The 10Mhz clock will be brought into the design by an input pin. The PCI Clock signal input pin is already present in the Phase 1 circuit, so this will be reused. FlexIO[65] (IO Channel 65) will be used to output the selected clock to the outside world.
// Clock Mux Circuit
wire LatchedFDt0, PCIClock;
d_flipflop inst6(FDt[0], PCIClock, WE_EXT[3], nc_rst, LatchedFDt0);
assign FlexIO[65] = LatchedFDt0 ? PXI10Mhz : PCIClock;
Clock Mux Circuit
FDt[0] is the first bit of the PCI data bus. This bit can either be 0 or 1, to indicate which clock source to choose. WE_EXT[3] is the 4th bit from the decoded PCI Address. When this bit is high, it indicates that the PCI Bus is addressing the 4th double word (byte offset 0xC) of the Register space for the GX3700. In our case, the value of this double word is used to select which clock is selected by our Mux.
At this point the design is complete, continue with the next sections to generate SVF or RPD files and load your design to the GX3700.