The PXI bridge FPGA contains the DMA engine for transferring data between the Flex FPGA and the PCI/PCIe host. Unlike a Scatter-Gather DMA engine, this one will need a contiguous memory space.
There are two 32-bit buses between the PXI bridge FPGA and the Flex FPGA for transmit and receive of DMA data.
For DMA write, the DMA controller will read data from the Flex FPGA and write this data to the host PC. The controller will only read data when it’s in DMA write mode and will only read when the EMPTY signal is de-asserted. The controller will only read up to the number of byte count specified for the DMA transfer and will not read more even if the FIFO is still empty.
For DMA read, the DMA controller will read data from the PC host and will write this data to the Flex FPGA. When in DMA read mode, the Flex FPGA must expect data and must store it. Otherwise, this data will be lost.
DMA FIFos Timing Diagram