The GX3700/GX3700e’s digital I/O signals are 5 volt tolerant. Logic families supported by the I/O interface include LVTTL, LVDS and LVCMOS. The FPGA’s I/Os includes 160 single ended I/O with support for 32 differential pairs, 4 dedicated global clock inputs (2 differential pairs), and various VCCIO voltages. At power up, all I/Os will be isolated from the UUT. The FPGA device supports up to four phase lock loops (PLL) for clock synthesis, clock generation and for support of the I/O interface. An on-board 80 MHz oscillator is available for use with the FGPA device or alternatively, the PXI 10 MHz or 100 MHz clock can be used as a clock reference by the FPGA.
The FPGA has access to all of the PXI Express bus resources including the PXI 10 MHz clock, PXIe 100 MHz clock, PXIe Sync100, PXIe DStar triggers, the local bus, and the PXI triggers; allowing the user to create a custom instrument which incorporates all of the PXI Express bus resources. The GX3700's FPGA has access to all of the PXI Hybrid slot compatible resources including PXI 10 MHz clock, the local bus, and the PXI triggers control and access to the FPGA is provided via the GX3700 / GX3700e’s driver which includes tools for downloading the compiled FPGA code as well as register read and write functionality.
The GX3700/GX3700e include the provision to add a daughter board which will provide additional flexibility for those users who wish to design their own custom interfaces for specific applications.
Communication between the customer-programmable FPGA and the PXI/PXIe bus is implemented via a dedicated FPGA device (Interface FPGA). The Interface FPGA contains control and status registers for the board and provides in-system programmability of the customer-programmable FPGA. The Interface FPGA interfaces directly to the PXI/PXIe bus and will decode/encode the bus protocol.
The GX3700 has external SRAM, flash, and an external clock source that is accessible by the customer.
The GX3700 employs the Altera Stratix III 780 pin device. Key features for the Altera device include:
47,500 logic elements (LEs) and 1.88 Mbits of memory.
Supports up to four phase-locked loops (PLLs) for clock synthesis, clock generation and support of I/O interfaces.
Up to five outputs per PLL can be accessed.
Dynamically reconfigurable logic supports programmable phase shift, frequency multiplication/division, and in-system frequency re-programming without reconfiguring the device.
Support for high-speed external memory interfaces including DDR, DDR2, SDR , SDRAM, and QDRII SRAM at up to 400 megabits per second (Mbps).
327 I/O pins arranged in eight I/O banks that support a wide range of industry I/O standards.
Supports up to 875 Mbps receive and 840 Mbps transmit LVDS communications data rates.
Support for Bus LVDS (BLVDS), LVDS, RSDS®, mini-LVDS and PPDS® differential I/O standards.
Supported I/O standards include LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X, LVPECL, LVDS, mini-LVDS, RSDS, and PPDS; PCI Express Base.
160 single ended I/Os.
32 differential pairs.
4 dedicated global clock inputs (2 differential pairs).
VCCIO can be preset using on-board jumpers to 1.2V, 2.5V, or 3.3V.
Internal FPGA SRAM (memory size depends on internal FPGA model installed).
1MB external SRAM in addition to internal FPGA SRAM.
8MB flash.
User controlled LED.
Integrated DMA engine.
All of PXI/PXIe instrumentation signals such as differential Star Trigger, SYNC100, CLK100, CLK10, local bus, trigger bus, and single-ended Star Trigger are available to customer.