Specifications

Logic Families

LVTTL, LVDS, configurable for 1.2 / 2.5 / 3.3 V logic; 5 volts compatible ( programmable via the FPGA on a per pin basis).

Output Current

+/ 12.0 mA, max. ( programmable via the FPGA on a per pin basis).

Input Leakage Current

±  10 uA.

Power On State

Programmable by line, default is disconnect at power on.

Number of Channels

4 banks of 40 I/O signals. Direction is configurable on a per pin basis Disconnect on a per bank basis.

Protection

Overvoltage: -0.5V to 7.0V (input) Short circuit: up to 8 outputs may be shorted at a time.

Daughter Board User Connectors

(4) SCSI III, VHDCI type, 68 pin female.

Board ID

4-bits.

Digital I/O

160, each bank of 40 can be configured to bypass or access the expansion board.

FPGA Flex I/O

4 signals.

Master Clear

From PXI interface.

Power

± 12 volts, +5 volts, +3.3 volts, +2.5 volts, +1.2 volts.

PXI 10 MHZ

PXI Bus.

Internal

80 MHz oscillator, ± 20 ppm.

FPGA Type

Default:

3700: Stratix III, EP3SL50F780.

3700e: Stratix III, EP3SL70F780.

Check the instrument panel, About page for newer versions.

Number of PLLs

Four.

Logic Elements

47,500.

Internal Memory

FPGA dependent:

EP3SL50: 2,133 Kb.

EP3SL70: 2,636 Kb.

EP3SL110: 4,875 Kb.

EP3SL150: 6,390 Kb.

EP3SL200: 10,646 Kb.

EP3SL340: 18,381 Kb.

EP3SE50: 5,625 Kb.

EP3SE80: 6,683 Kb.

EP3SE110: 8,727 Kb.

EP3SLE260: 16,282 Kb.

3.3 VDC

400 mA (typ.);  1 A (Max.)

5 VDC

300 mA (typ.);  1.2 A (Max.)

12 VDC (For Expansion Board)

Expansion Board Dependent.

Operating Temperature

0 to 50° C.

Storage Temperature

-20° C to 70° C.

Size

3U PXI.

Weight

200 g.