The GX5296 system uses several clocking signals to generate and capture digital vectors from the I/O Channels.
The figure below provides an overview of the GX5296’s clock architecture.
Clock Architecture Overview
The system clock (T0) defines the edge or timing resolution as well as the vector rate. The maximum clock rate is 125 MHz. The clock generator employs a PLL which uses the PXI 10 MHz as its reference. A total of 8 phases and 4 windows are generated by the timing system and are available for supporting drive and sense data respectively. Each phase consists of an assert and de-assert edge and each window provides the ability to capture data on an open or close window edge. The 8 phases and 4 windows are available for mapping edge timing to a specific channel. Up to 64 unique time set groups can be defined for a burst and are selectable on a per sequence step basis. A time set group consists of up to 8 phases and 4 windows. Additionally, six data formats are supported - NR (no return), R0, R1, RHiZ, and RC (Return to Complement), RSC (Return Surround with Complement). Data formatting is assigned on a per channel basis and is used in conjunction with the phase and window timing edges.
The T0 clock has a period programming resolution of 250 ps. This resolution is also the timing edge resolution for the 8 phases and 4 windows. A minimum assert / de-assert time of 4 ns must be observed for a phase and window.
The System Clock provides the timing for phase, windows, and the sequencer. The System Clock also generates the Vector Clock which is used to define a Vector’s period.
The Vector Clock is derived from the System Clock and the Clocks per Vector (CPV) setting. The Vector Clock period will equal the System Clock Period multiplied by the Clocks per Vector setting which can be programmed from 1 to 256. The Vector Clock is used to clock out Vectors from memory when the Sequencer is running. The value of CPV can be changed per sequence step, provided the T0 clock period is > 50ns. For shorter periods, CPV must be a static value for the entire burst. Note also that the range of phase and window edge values is equal to the vector period. For example, if the T0 clock period is 10ns, and CPV is 10, then the phase and window edge timing range will be 0 to 100 ns. Using a high value of CPV with a high frequency T0 will yield the best edge resolution.
See GtDio6xStepSetClock in the functions reference chapter for information.