Architecture Block Diagram
The master clock functional block includes a fixed 500 MHz master clock oscillator and a Frequency Synthesizer which may be used instead of the 500 MHz oscillator. The reference clock for the Frequency Synthesizer can use the built-in 20 MHz oscillator, PXI Clock 10 MHz or an external oscillator in the range of 5 to 80 MHz.
Using the Master Clock as a basis, the Timing Generator block produces Phase, Window, Vector and System clock signals. In a Master/Slave configuration, these signals are broadcast across the PXI Backplane (B/P) on the Local Bus signal lines to other board sequencers. The System clock is used by the sequencer to start each phase and window along with incrementing the Vector and Record memories. The System clock can be sourced from the internal T0 clock or an external source connected to an auxiliary channel.
The Step Memory defines the order in which Vectors will be driven or sensed (recorded). This block provides the addressing to the Vector Memory and the Record Memory. The Step Memory also contains the T0 Clock period, Phase, Window, CPV (clocks per vector) and a Control statement for conditional jumping and looping.
The stimulus, expect, and Tri-State data for each vector and channel is stored in the Vector Memory.
The Record Memory stores individual channel error results or raw response data depending on the current Step’s record mode.
The test logic monitors Auxiliary Channels, Error signal, Channel Test signals, and PXI triggers and provides the Sequencer Engine with input for its conditional logic.
The auxiliary I/O block offers a range of useful user and diagnostic input and output signals for user applications. The inputs may be used for synchronizing or triggering the GX5960 with UUT generated events. Note that the Aux I/O functions are only present on the GX5961 board.
The channel I/O block takes the Stimulus data, applies the data format and outputs the formatted data according to the phase timing. The resultant Drive and Enable signals go to the Channel Drivers (pin electronics).
The Response High and Response Low signals from the Receivers are examined and based on the window timing and capture mode and the response is analyzed with respect to the Expect data. The cumulative Error signal goes to the Test Logic block so it can be used for Jumping, Halting and Counting of Errors.