Output Data Block Diagram
The figure above is a block diagram of a single I/O pin. Up to 16 boards can be used in one domain for a maximum of 512 pins (each board containing 32 I/O pins). Output data, which is stored in the Vector memory, is outputted from the board as a function of the PHASE signal through the Driver when enabled; the encoded data (see Memory Management) enables the Driver output when the specified Vector is defined as an output Vector. The output data to the UUT will also be stored in the Record memory via the receiver pin electronics. The output data will be formatted as it was defined programmatically by the user to one of the following formats: No Return, Return to Zero, Return to One, Return to Hi-Z, Return to Complement, Surround Complement.
Each data channel’s output signal has programmable Drive Out Hi and Drive Out Lo levels. The Drive Out Hi level can be set from -9 volts to +15 volts and must be greater than the output driver’s Drive Out Low voltage. The Drive Out Low voltage can be set from -10 volt to +11 volts. These levels are based on a Vcc voltage of +18 volts and a Vee voltage of -14 volts. Total range for the driver and comparator voltage range is -14 V to +29 volts inclusive with a maximum span of 24 volts. Each Driver channel slew rate can be programmed, with rising and falling slew rates programmed independently.
Each Driver has output over current protection. Once an over current condition occurs, the output will be set automatically to Hi-Z impedance. The over current event can be monitored by the CPU as well as cleared under CPU control in order to re-enable the output.
The pin electronics input analog stage is comprised of a set of input pull-up and pull down resistive loads, constant current sink and source loads, and clamping (commutation) sink and source voltages. The input pull-up and the pull down resistive loads can be set to one of the following values, 240 Ohms, 290 Ohms, 1 KOhms or no load. The input resistive load is useful in applications with very low DUT output swings (where a traditional active load will not switch on and off completely or quickly) and also as a means of forcing the DUT to a known voltage when the DUT is in a Hi-Z state. In addition, the input channel programmable load can be set to have constant source and sink current loads up to 24 mA each with 0.3662 μA of resolution. The input channel’s current source will force the specified constant current to be active when the input voltage is above the high voltage clamp value. The input channel’s current sink forces the specified constant current to be active when the input voltage is below the low voltage clamp value.
The input signal is connected to two comparators. The threshold sense high and low voltage levels are set programmatically by the user. Both the input high and low voltage threshold values can be set from -10.0V to +11.0V. These levels are based on a Vcc voltage of +18 volts and a Vee voltage of -14 volts. The sense hi level must be higher than the input low voltage threshold and the input low voltage threshold must be lower than the input high voltage threshold. Maximum voltage range is -15 V to +26 V. Each channel’s operating temperature, the Vcc / Vee voltage rails, drive high / drive low voltages, sense hi / sense lo voltages, and output current values can all be monitored and measured.
Input data is stored in the Record Memory and is stored at the rate of the Vector Clock. The Vector opcode, once decoded, (see Memory Management) enables the input when the specified step is defined as an input step.
The input data will be processed as follows:
● If input data is higher than the high voltage threshold, the input is detected as logic high. Data will be logged as logic high to record memory or a 0 is logged if operating in real time compare mode.
● If input data is lower than the low voltage threshold, the input is detected as a logic low. Data will be logged as a logic low to the record memory or a 0 is logged if operating in real time compare mode.
● If input data is higher than a low voltage threshold and lower than a high voltage threshold, input is invalid. Data will be logged as a logic low to the record memory or logged as a 1 if in real time compare mode.
Note: Each channel’s output and input are connected. As a result a channel’s output will be recorded in the record memory if the step is set to response recording.
Each input channel’s constant current source and sink load currents and its corresponding voltage clamps can be set programmatically.
The input channel’s current load provides a constant current load that is active when the input voltage is above or below the high voltage or low voltage clamp values respectively. The input channel’s constant current source value can be set from 0mA to 24mA with 0.3662 μA of resolution.
With independent high and low clamping (commutating) voltages, the source and sink currents each have their own threshold voltage. If the voltage on the channel input, when the load is activated, is between the two clamping voltages, the load will remain in a high impedance state (see Figure 4-18).
The input channel’s source and sink constant currents can be read back and set dynamically at any time even when the DIO is in its run state.
GX5960 Input Load Current Voltage Clamps
The input channel’s high and low clamping (commutating) voltage values can be set from -10V to +11V when the Vcc and Vee rail voltages are set to +18 volts and -14 volts respectively. Maximum range for the Vcom voltages is -5V to +26V.
The input channel’s constant current voltage clamps can be read back and set dynamically at any time even when the DIO is in its run state.
Each input channel‘s load may be configured as a selectable resistor with pull-up and pull-down values. The resistive load is useful in applications with very low DUT output swings (where a traditional active load will not switch on and off completely or quickly) and also as a means of forcing the DUT to a known voltage when the DUT is in a Hi-Z state. When the resistive load is applied to a UUT the Hi-Z state, the DIO input maintains a low leakage current when the UUT input voltage is between the VCC and VEE supply values. The following are the resistive load options:
Pull-up |
Pull-down |
Open (Hi-Z) |
Open (Hi-Z) |
250 Ohm |
250 Ohm |
290 Ohm |
290 Ohm |
1 K Ohm |
1 K Ohm |
Resistive Load Options
The input channel’s pull-up and pull down resistive loads can be read back and set dynamically at any time even when the DIO is in its running state.
Each channel has a high-speed dual voltage comparator with its own independent threshold setting. Each channel’s high and low input voltage threshold comparators can be set programmatically. There are two threshold voltage level settings for each input channel: logic high level and logic low level. Each input channel can detect three voltage levels: High, low and undefined. When the input voltage is equal or greater than the threshold logic high, a logic high is recorded. When the input voltage is equal or less than the threshold logic low, a logic low is recorded. When the input voltage is between the threshold high level and the threshold low setting then the value is recorded as an in-valid logic level.
The input high and input low voltage thresholds can operate over a range from -15V to +26V with the high threshold higher than the input low voltage threshold and the low voltage threshold lower than the input high voltage threshold.
The Input channel’s low and high threshold voltages can be read back and set dynamically at any time even when the DIO is in the run state.
Each output channel’s data can be formatted in five different ways:
● No Return: The output logic level stays either high or low for the duration of the clock period (default).
● Return to Zero: The signal returns to zero during the phase return edge within a clock cycle.
● Return to One: The signal returns to one during the phase return edge within a clock cycle.
● Return to Hi-Z: The signal returns to Hi-Z during the phase return edge within a clock cycle.
● Return to Complement: The Return to Complement (also called Manchester code) format ensures that each transmitted data bit has at least one transition during the phase return edge within a clock cycle. It is, therefore, self-clocking, which means that a clock signal can be recovered from the encoded data. Return to Complement ensures frequent data transitions which are directly proportional to the clock rate which helps clock recovery. A logic low is expressed by a low-to-high transition. A logic high is expressed by high-to-low transition. The transitions which signify logic high or low occur at the midpoint of a period, the direction of the mid-bit transition indicates the data.
● Compliment Surround: Tristate driver from beginning of vector to assert time and then drive programmed level. Tristate driver at return time.
● Force Zero: Force driver to low level.
● Force One: Force driver to high level.
● Force Off: Force driver to Hi-Z.
● Force Inverted Phase: Drive high to low at the phase assert edge and low to high at the phase return edge.
● Force Phase: Drive low to high at the phase assert edge and high to low at the phase return time.
Note: the specified channel data format will be applied to all the channels’ vectors that are set as outputs. The inputs do not support or decode formatted data.
Each output channel has independent adjustments for the rising and falling edge slew rates.
The driver output stage also has a programmable bias current which can be used to manage overall power consumption of the PEs, i.e. lower bias current settings can be used for lower data rate / edge rate applications. Note that the slew rate will be affected by the bias current settings. The slew rate range is programmable from 0.1 V/ns to 1.0 V/ns with a high bias current setting. The channels’ slew rates can be read back and set dynamically at any time even when the DIO is in the run state.
Each output channel’s low and high level drive voltages can be set programmatically. Each output channel’s driver has two levels, low and high. The total output driver voltage swing (output driver high voltage less output driver low voltage) is limited to 25V per channel.
The output channel’s driver voltages can be read back and set dynamically at any time even when the DIO is in the run state.
Each digital channel includes a parametric measurement unit (PMU) which can be used to characterize and measure a digital pin’s DC characteristics. The PMU can be configured for force current, measure voltage, or force voltage, measure current. The PMU’s range of operation is listed below:
Force voltage range: -10 volts to +15 volts (for Vcc = +18V and Vee = -14V).
Force current range: +/- 25 mA FS or +/- 200 mA FS.
Measure voltage range: -10 volts to +15 volts (for Vcc = +1v and Vee = -14V).
Measure current range: +/- 25 mA FS or +/- 200 mA FS.
Measurement resolution is 16 bits for both voltage and current measurement functions. Note that while each channel has a dedicated PMU, the measurement resource is shared between all 32 channels, requiring sequential measurement of each channel.