Timing Sets

The GX5960 Timing Subsystem is comprised of the System Clock, the Vector Clock and a Timing Generator which generates the Phase Assert, Phase Return, Window Open, and Window Close signals. The System Clock Cycle determines the base frequency at which Vectors are assigned to the currently running Step which will be clocked from the Vector Memory. The Vector Clock is derived from the System Clock, and is controlled by the Clocks per Vector setting. The Vector Clock period is equal to the System Clock period multiplied by the Clocks per Vector. The Phase and Window signals determine how and when (in conjunction with the Data Format) a Vector’s output state will be applied to the I/O Pins within a System /Vector Clock cycle. The Phase Trigger Source setting determines which clock (System or Vector) will cause the Phase signal to reset and begin again.

A timing set consists of one Phase and Window; there can be up to four timing sets per index number. The timing sets are used to control the channel drivers and receivers.

Phase

A Phase controls the driver output operation and consists of an Assert and a Return edge. The Assert signal loads the current pattern code in to the output driver. The Return signal is used to enable the format code in the driver. The Return signal is not used for the Non Return format code. 

Window

The Window controls the signal capture for the receiver and consists of an Open and Close edge. Each channel can be set to one of three capture modes. In Windowed mode, the Window Open signal begins signal capture and the Window Close ends the capture. In Open Edge mode, the Window Open edge strobes the channel comparator input and the Close Edge is ignored. In Close Edge mode, the Window Close edge strobes the channel comparator input and the Open Edge is ignored.

The Phase timing logic can be triggered by either the System Clock or the Vector Clock. The Window timing logic is triggered by the Vector Clock.

A timing diagram of the System Clock, Vector Clock, Window, and Phase signals is shown in the figure below:

System Clock, Vector Clock, Phase and Window Timing Diagram

Indexed Timing

Each Sequencer Step can be programmed to point to any of the 256 timing sets located in the Timing Set Index Memory. Each timing set is composed of four pairs of Phase and Window settings as follows:

Components of a single Timing Set

The user can assign one of the four timing set’s Index number to any I/O channel or a range I/O channels. The Timing Set to I/O channel assignment relationship will be maintained and applied to every Step / Timing Set in Step Memory. Timing set index is programmed per Step. Each channel can be set to use any of the four Phase Assert and Phase Return pair, as well any of the Window Open and Window Close pairs. E.g. Channel 1 can have TSet 0 for Phase Assert and Phase Return, and TSet 2 as the Window Open and Window Close. Then each step can be assigned different timing by using one of the 256 Timing Set Index numbers, while the channels will maintain the Phase and Window TSet settings. The following figure details how the timing set index memory is used with the sequencer step memory and the four pairs of time sets:

Indexed Timing Mode Diagram

Note: that the TSet used (one of four) is assigned to each channel and is fixed The timing set used is assigned per step and is variable based on the values in the timing set index memory. Timing Set rules for valid timing set signal operation are detailed below and are based on the Master Clock operating at 500 MHz.

●     Phase pulse width must be greater than 3.5 clocks, i.e., the Return value must be at least 4 clocks more than the Assert value, when operating with the 500 MHz clock. (2nS * 4 using the 500MHZ clock).

●     Window pulse width must be greater than 3.5 clocks, i.e., the Close value must be at least 4 clocks, when operating with the 500 MHz clock.  (2nS * 4 using the 500MHZ clock).

Timing Set Rules

●     End of Vector period Dead Time.  The Phase Return, Window Close and Window Open edges must occur before the end of the Vector period to allow for Domain Error propagation delay. During this delay errors are not recorded or processed, this delay is referred to as Dead Time; this occurs when the Error Count memory and Error Address memory are updated or a Halt on Error pause is enabled. The Phase return edge has a minimum of 8ns (using the 500MHZ clock) of Dead Time regardless of the number of boards comprising a domain. The Window capture edge (Open, Close or Windows) Dead Time is dependent on the number of boards that comprise a domain. The Dead Time range for various board configurations is detailed in the table below and is applicable when operating in real time compare mode.

RO = Record Offset

Dead Times for the Real Time Compare Mode

Note: The record offset (RO) value allows the user to shift the record signals (pattern code expect, mask, and window strobes) to be aligned with the drive data or expect data timing due to system and UUT delays. The record offset resolution is the master clock’s period and has a range from 0 to 63 MCLKs.

Phase and Window Dead Time Diagram

Note: Phases and windows can extend to the System clock period times the number of clocks per pattern minus the dead time.