The GX5960 has a unified Vector memory which combines several pieces of information. Each Vector channel state is represented in the form of an ASCII character. The ASCII Character encodes the Output, Real Time Expect, Tristate Control (Direction), and Mask information for a particular channel within a Vector. The Vector Memory API functions allow the user to write and read from Vector Memory to any desired channel or group of channels for a given range of Vectors.
A separate Record Memory contains either response data or error data depending on the Record Mode selected for a particular Step. If the Step’s Record Mode is set to Response, a ‘1’ indicates a logic high response, and a ‘0’ indicates a logic low response. If the Step’s Record Mode is set to Error, a ‘1’ indicates a real time compare error, and a ‘0’ means no real time compare error occurred. The Record Memory stores up to 256K of response vectors. The indices of the Record Memory are mapped 1 to 1 with the Vector Memory.
Opcode |
Description |
Driver State |
Drive Level |
Comparator Expect |
Invert Code |
1 |
Drive High, Don’t Expect (Don’t Care) |
On |
VoH |
None |
Drive Low ‘0’. |
0 |
Drive Low, Don’t Expect (Don’t Care) |
On |
VoL |
None |
Drive High ‘1’. |
h |
Drive High, Expect High |
On |
VoH |
>ViH |
Drive Low, Expect Low ‘l’. |
l |
Drive Low, Expect Low |
On |
VoL |
<ViL |
Drive High, Expect High ‘h’. |
H |
Expect High, Don’t Drive |
Off |
X |
>ViH |
Expect Valid Low ‘L’. |
L |
Expect Low, Don’t Drive |
Off |
X |
<ViL |
Expect Valid High 'H'. |
Z |
Tristate (Disabled) |
Off |
N/A |
None |
Disable Channel ‘Z’. |
/ |
Drive Low, Expect High |
On |
VoL |
>ViH |
Drive High, Expect Low ‘\’. |
\ |
Drive High, Expect Low |
On |
VoH |
<ViL |
Drive Low, Expect High ‘/’. |
V |
Expect Valid Level |
Off |
X |
>ViH OR <ViL |
Expect Invalid ‘B’. |
B |
Expect Invalid Level |
Off |
X |
<ViH AND >ViL |
Expect Valid ‘V’. |
R |
Repeat previous opcode |
Repeats the last non repeat/invert code. |
|||
I |
Invert previous opcode |
Inverts the last non repeat/invert code. Refer to Invert Code |
|||
C |
Collect CRC |
Off |
X |
None |
Collect CRC ‘C’. |
Vector Opcode Description Sequencer Step Memory
When running, the Sequencer executes a series of one or more Steps, as defined by the user. This execution is known as a Burst. The Burst will continue until a non-jumping Step is executed with the Last Step flag set to True. At this point, the Sequencer will enter the Finish or Idle Step (see Finish/Idle State) A Step points to a block of vectors (contiguous, in vector memory) and applies timing, control, and record parameters during run-time.
Each Step can be assigned a block of vectors from the vector memory. The Step contains the number of vectors and the start offset (from Vector memory 0) address. Steps can have overlapping or identical vector assignments (offset location and number of Vectors). Note that the vector offset must be a multiple of 4.
See GtDio6xStepSetVectorCount in the functions reference chapter for more information.
Each Step contains a programmable value for the Vector Clock period (T0 Clock). The Vector Clock period is programmed in terms of of the selected (Master Clock or Frequency Synthesizer) clock period. When using the default 500 MHz onboard Master Clock, the resolution is 2nS.
When the System Clock source is set to the internal T0 CLK, the System Clock period setting will be based on ½ of the Master Clock period.
For example if the Master Clock is set to 500 MHz, then a setting of 20 would be:
20 * (1/2 (2ns)) = 20ns.
With a Master Clock of 100 MHz edge resolution would be;
20 * (1/2 (10ns)) = 100ns.
The valid setting values for T0 CLK are from 20 to 65550 and must be a multiple of two.
See GtDio6xStepSetClock in the functions reference chapter for more information.
Each Step contains Time Set information which defines the Phase Assert/Return, and Window Open/Close edges. This setting is in terms of ½ Master Clock cycles. When using the default 500 MHz onboard Master Clock, the resolution is 1nS.
The number of Timing Sets available per Step, and the way to configure them is described in the Timing Mode section of this chapter.
See GtDio6xStepSetTimingSets, GtDio6xStepSetTimingSetIndex for more information.
Two clocks are available for triggering the phase’s and window’s timing, System Clock and Vector Clock.
The Clocks per Vector determines the number of System Clocks that will be generated for each Vector Clock. When Clocks per Vector = 1, the Vector Clock period is equal to System Clock period. When Clocks per Vector = 2, the Vector Clock period is two times the System Clock period.
Timing Diagram of Clocks per Vector at 1
Timing Diagram of Clocks per Vector at 2
Timing Diagram of Clocks per Vector at 3
See GtDio6xStepSetClock for more information.
Each Step can be configured to use the Record Memory in a specific manner.
The Step can be configured to record a response or perform a real time compare and record error states.
The user can also choose to not write to the record memory. The following describes the various record modes:
None - All three record memories are disabled.
Record Count - The Error Count and Error Address Memory are enabled.
Record Error - All three memories are enabled and the Record Memory is set to record error data.
Record Response - All three memories are enabled and the Record Memory is set to record response data.
See GtDio6xStepSetRecordMode for more information.
The user is allowed to select the Phase Trigger source to be the System Clock or Vector Clock for each phase in every step. The Phase trigger source changes the behavior of formatted output signals to allow multiple transitions per cycle. See GtDio6xStepSetPhaseTriggerSource for more information.
The phase reset source allows the user to select the phase reset signal source which can be the System Clock or the Vector Clock. The phase reset signal restarts the phase assert and return timing.
See GtDio6xStepSetPhaseTriggerSource for more information.
This flag indicates whether the current step is the last step of the sequence burst or a sub-step of a multi step burst.
See GtDio6xStepSetLast for more information.
There is one control statement that is evaluated at the end of each Step by the Sequencer. The control statement is part of the Step’s memory structure. At the end of a Step (where one or more Vectors were executed), a control statement allows the Sequencer to Jump, Go to Subroutine, Loop, Stop, or Continue to the next Step. The branching can be made on the following conditions:
· Always – Always evaluate the conditional statement as True.
· Not Pass – Conditional statement is True if the Step has not Passed.
· Not Fail – Conditional statement is True if the Step has not Failed.
· Fail – Conditional statement is True if the Step has failed.
· Pass – Conditional statement is True if the Step has passed.
· Burst Fail – Conditional statement is True if the Burst failed.
· Burst Pass – Conditional statement is True if the Burst passed.
· Control Resource 0 – Conditional statement is True if Control Resource 0 is True.
· Not Control Resource 0 – Conditional statement is True if the Control Resource is Not True.
· Control Resource 1 – Conditional statement is True if the Control Resource 1 is True.
· Not Control Resource 1 – Conditional statement is True if the Control Resource 1 is Not True.
· Control Resource 2 – Conditional statement is True if the Control Resource 2 is True.
· Not Control Resource 2 – Conditional statement is True if the Control Resource 2 is Not True.
· Control Resource 3 – Conditional statement is True if the Control Resource 3 is True.
· Not Control Resource 3 – Conditional statement is True if the Control Resource 3 is Not True.
See GtDio6xStepSetControl for more information.