The GX1110 contains a PXI interface device as well as an FPGA which is configured to support DDS or AWG operation which essentially provides all of the digital logic for waveform generation. Configuration of the FPGA is performed at power up or via a driver function call prior to programming the module’s waveform generation parameters.
Analog components include a 12-bit D to A converter as well as a programmable offset generator, a programmable output amplifier, and multi-pole low pass filters. The output stage is common for both DDS and AWG operation modes with different filters to optimize noise and spectral performance, based on specific mode of operation.
The AWG includes sequence and a waveform memory configured as 2M by 12 bits. A PLL based clock generator provides a programmable sample clock rate from 10 mHz to 100 MHz with a resolution of 4 digits or .01 Hz - whichever is lower. The minimum waveform sequence length is 4 points. Waveform sequencing includes the ability to loop continuously, loop once, sequence between defined start and stop addresses or loop (burst) N times. The output is filtered by a 3-pole, 35 MHz, low pass Bessel filter.
The DDS mode of operation requires that the FPGA be reconfigured to support 2K by 12 bits waveform memory. Standard waveforms are loaded into the waveform memory when the FPGA is configured, eliminating memory load times at run-time. Standard waveforms include sine, triangle, ramp (up or down), pulse, square and noise. The DDS generator operates at a fixed 160 MS/s and generates frequencies from 10uHz to 30 MHz with resolution of 10 uHz. The output is filtered by a 6-pole, 35 MHz, low pass elliptical filter. The figure below shows the GX1110 with its front panel connectors.
GX1110 Board Side View