The Figure below illustrates the GX1642/GX1648 board’s common static voltage architecture. The board is programmed by software using the PXI bus interface to set the group’s range, D/A output and update control, and control of the board’s 4 digital I/O pins. The 78-pin connector on the right (J3) provides the interface to the D/A’s outputs, digital output and input signals, and the external update signals.
GX1642/GX1648 Block Diagram
The figure illustrates the GX1649 board’s architecture. The board includes an ARB circuit and memory for each Group (A to D) as well as a DIO sequencer that interfaces with the 8 TTL I/O Channels. Each of the 64 channels can function has a static analog output or as an ARB.
GX1649 Block Diagram
The figure below illustrates the GX1632e board’s architecture. The GX1632e consists of various sections: PXIe Interface, FPGA, DDR3 Memory, Power Supplies, DAC and OPAMP blocks.
1. The PXIe interface connects the card to a PXIe backplane, which is in turn connected to a CPU allowing the user to control the GX1632e. XJ4 connects the PXI trigger bus to the control. The trigger bus allows the board to be trigger by one or more signals on the PXI bus.
2. The FPGA controls communication between the user and the GX1632e operation including the Interface Logic for PCIe Gen 2 x4 interface, DMA controller for data streaming, Memory controller for DDR3, and DAC control for channel outputs.
3. The Power Supply provides ±28V for the output OPAMPs, 2.5V for FPGA I/O and the DACs, 1.5V for DDR3, 1.1V and 1.2V for FPGA power.
4. Two 4 Gb DDR3 Memory configured as 256Mx16.
5. Each DAC block represents one group of 8 channels. Each group has dedicated control lines with two sets of address and data lines shared between two groups.
6. Each output channel is driven by a power OPAMP that has a capability of outputting 10mA maximum.
GX1632e Block Diagram