TANGO Test Log

Company : THALES AIR DEFENCE
Project : TANGO Aquila Test Bench
Program : STAR_DG_NR_TEST
Serial Number : 10433
Start Time : 12/11/13   09:06:56

Task 2 : CKTST 2 : POWER SUPPLY TEST

# Name Pin Unit Min Max Result Status
001 test 2_1 : +5 V voltage short circuit P1-36/P1-37 Ohm 300.000 361.942 Pass
002 test 2_2 : +15 V voltage short circuit P1-40/P1-41 Ohm 300.000 356.364 Pass
003 test 2_3 : -5,2 V voltage short circuit P1-46/P1-47 Ohm 30000.000 33266.200 Pass
# Name Pin Unit Tolerence Value Result Status
004 test 2_4 : +5 V current level P1-36/P1-37 Amp +/ -0.200 0.860 1.031 Pass
005 test 2_5 : +15 V current level P1-40/P1-41 Amp +/ -0.050 0.531 0.554 Pass
006 test 2_6 : -5,2 V current level P1-46/P1-47 Amp +/ -0.050 0.153 0.178 Pass
007 test 2_7 : +5 V power supply voltage P1-36/P1-37 Volt +/ -0.250 5.000 5.240 Pass
008 test 2_8 : +15 V power supply voltage P1-40/P1-41 Volt +/ -0.750 15.000 15.202 Pass
009 test 2_9 : -5,2 V power supply voltage P1-46/P1-47 Volt +/ -0.250 -5.200 -5.190 Pass

Task 3 : CKTST 3 : J3, J4, J7 AND J9 OUTPUT TEST

# Name Pin Unit Tolerence Value Result Status
001 test 3_1A : J3 (H30_REF_1) output power test J3 dBm +/ -1.000 2.000 3.172 Fail*
002 test 3_1B : J3 (H30_REF_1) frequency test J3 MHZ +/ -0.100 31.080 31.080 Pass
011 test 3_5 : J7 (HCD_RES_OUT) output clock delay test J7 uSec +/ -0.150 1.500 1.499 Pass
012 test 3_6 : J9 (H20_RES_OUT) output clock delay test J9 nSec +/ -70.000 720.000 759.609 Pass

Task 3 : CKTST 3 : J3, J4, J7 AND J9 OUTPUT TEST

# Name Pin Unit Tolerence Value Result Status
001 test 3_1A : J3 (H30_REF_1) output power test J3 dBm +/ -1.000 2.000 3.183 Fail*
002 test 3_1B : J3 (H30_REF_1) frequency test J3 MHZ +/ -0.100 31.080 31.079 Pass
003 test 3_2A : J4 (H30_REF_2) output power test J4 dBm +/ -1.000 10.000 10.385 Pass
004 test 3_2B : J4 (H30_REF_2) frequency test J4 MHZ +/ -0.100 31.080 31.080 Pass
# Name Pin Unit Min Max Result Status
005 test 3_3A1 : J7 (HCD_RES) output clock TTL high level test J7 Volt 1.600 3.013 Pass
006 test 3_3A2 : J7 (HCD_RES) output clock TTL low level test J7 Volt 0.800 0.047 Pass
# Name Pin Unit Tolerence Value Result Status
007 test 3_3B : J7 (HCD_RES) frequency test J7 MHZ +/ -0.100 1.295 1.295 Pass
# Name Pin Unit Min Max Result Status
008 test 3_4A1 : J9 (H20_RES_OUT) output clock TTL high level test J9 Volt 1.600 9.99999e+037 Pass
009 test 3_4A2 : J9 (H20_RES_OUT) output clock TTL low level test J9 Volt 0.800 -0.002 Pass
# Name Pin Unit Tolerence Value Result Status
010 test 3_4B : J9 (H20_RES_OUT) frequency test J9 MHZ +/ -0.100 20.720 20.714 Pass
011 test 3_5 : J7 (HCD_RES_OUT) output clock delay test J7 uSec +/ -0.150 1.500 1.499 Pass
012 test 3_6 : J9 (H20_RES_OUT) output clock delay test J9 nSec +/ -70.000 720.000 759.156 Pass

Task 3 : CKTST 3 : J3, J4, J7 AND J9 OUTPUT TEST

# Name Pin Unit Tolerence Value Result Status
001 test 3_1A : J3 (H30_REF_1) output power test J3 dBm +/ -1.000 2.000 3.190 Fail*
002 test 3_1B : J3 (H30_REF_1) frequency test J3 MHZ +/ -0.100 31.080 31.080 Pass
003 test 3_2A : J4 (H30_REF_2) output power test J4 dBm +/ -1.000 10.000 10.365 Pass
004 test 3_2B : J4 (H30_REF_2) frequency test J4 MHZ +/ -0.100 31.080 31.079 Pass
# Name Pin Unit Min Max Result Status
005 test 3_3A1 : J7 (HCD_RES) output clock TTL high level test J7 Volt 1.600 3.030 Pass
006 test 3_3A2 : J7 (HCD_RES) output clock TTL low level test J7 Volt 0.800 0.047 Pass
# Name Pin Unit Tolerence Value Result Status
007 test 3_3B : J7 (HCD_RES) frequency test J7 MHZ +/ -0.100 1.295 1.295 Pass
# Name Pin Unit Min Max Result Status
008 test 3_4A1 : J9 (H20_RES_OUT) output clock TTL high level test J9 Volt 1.600 4.350 Pass
009 test 3_4A2 : J9 (H20_RES_OUT) output clock TTL low level test J9 Volt 0.800 -0.040 Pass
# Name Pin Unit Tolerence Value Result Status
010 test 3_4B : J9 (H20_RES_OUT) frequency test J9 MHZ +/ -0.100 20.720 20.708 Pass
011 test 3_5 : J7 (HCD_RES_OUT) output clock delay test J7 uSec +/ -0.150 1.500 1.500 Pass
012 test 3_6 : J9 (H20_RES_OUT) output clock delay test J9 nSec +/ -70.000 720.000 759.410 Pass