TANGO Test Log


Company : THALES AIR DEFENCE
Project : TANGO Aquila Test Bench
Program : TRAC_DIGITAL_GENERATION_TEST
Serial Number : No Serial Number
Start Time : 12/06/13   10:51:54

Task 8 : CKTST 8 : J1 OUTPUT SIGNAL FREQUENTIAL TEST

# Name Pin - Value - Result Status
001 test 8_1 : J1 output signal (with bus-ci = 00 H) J1 - "Correct" - "Correct" Pass
006 test 8_6 : J1 output signal (with bus-ci = 05 H) J1 - "Correct" - "Correct" Pass
007 test 8_7A : J1 output signal (with bus-ci = 06 H) J1 - "Correct" - "Correct" Pass
# Name Pin Unit Tolerence Value Result Status
008 test 8_7B : J1 output signal 0.3dB bandwidth(with bus-ci = 06 H) J1 MHZ +/ -0.120 0.400 0.519 Pass
# Name Pin - Value - Result Status
009 test 8_8A : J1 output signal (with bus-ci = 07 H) J1 - "Correct" - "Correct" Pass
# Name Pin Unit Min Max Result Status
010 test 8_8B : J1 output signal parasites strip test (with bus-ci = 07 H) J1 dBc 70.000 71.902 Pass

Task 3 : CKTST 3 : J3, J4, J7 AND J9 OUTPUT TEST

# Name Pin Unit Tolerence Value Result Status
001 test 3_1A : J3 (H30_REF_1) output power test J3 dBm +/ -1.000 2.000 3.065 Fail*
002 test 3_1B : J3 (H30_REF_1) frequency test J3 MHZ +/ -0.300 31.080 31.080 Pass
003 test 3_2A : J4 (H30_REF_2) output power test J4 dBm +/ -1.000 10.000 10.177 Pass
004 test 3_2B : J4 (H30_REF_2) frequency test J4 MHZ +/ -0.300 31.080 31.080 Pass
# Name Pin Unit Min Max Result Status
005 test 3_3A1 : J7 (HCD_RES) output clock TTL high level test J7 Volt 1.600 6.000 3.079 Pass
006 test 3_3A2 : J7 (HCD_RES) output clock TTL low level test J7 Volt 0.800 0.047 Pass
# Name Pin Unit Tolerence Value Result Status
007 test 3_3B : J7 (HCD_RES) frequency test J7 MHZ +/ -0.010 1.295 1.295 Pass
# Name Pin Unit Min Max Result Status
008 test 3_4A1 : J9 (H20_RES_OUT) output clock TTL high level test J9 Volt 1.600 6.000 4.280 Pass
009 test 3_4A2 : J9 (H20_RES_OUT) output clock TTL low level test J9 Volt 0.800 0.000 Pass
# Name Pin Unit Tolerence Value Result Status
010 test 3_4B : J9 (H20_RES_OUT) frequency test J9 MHZ +/ -0.200 20.720 20.714 Pass
011 test 3_5 : J7 (HCD_RES_OUT) output clock delay test J7 uSec +/ -0.150 1.500 1.477 Pass
012 test 3_6 : J9 (H20_RES_OUT) output clock delay test J9 nSec +/ -70.000 720.000 760.000 Pass

Task 5 : CKTST 5 : EXTERNAL PHASE TEST