The following are key GC5050 characteristics and architecture:
● The GC5050 is a Plug and Play (PnP) board. The operating system such as Windows automatically identify and arbitrate resource requirements as well as notify the user that a new board was found and automatically install the driver for it.
● A DIO domain, when in RUN mode, operates independently of the host computer.
● Each GC5050 DIO board supports a maximum clock frequency of up to 50 MHz per channel for all channels (total of 1.6GB of data per second for 256 channels).
● A GC5050 (Master) board controls the timing of a DIO domain and can be synchronized to a UUT.
● Multiple Master boards are used to synchronize mutually asynchronous UUT elements.
● Each GC5050 Slave board adds 32 UUT channels. Up to seven Slave boards can be added to make a total of 256-channel domain.
● DIO boards can support different interfaces (that is different voltage levels) by mounting different I/O Modules (see the GT I-O Modules and Interfaces User's Guide).
● Every GC5050 board, Master or Slave, require an I/O Module daughter card.
● Channel direction is controlled in-groups of eight. Direction can be set while in RUN mode for each step, input or output as defined in the loaded vector.
● GC5050 output channels can be enabled or disabled dynamically by external lines in groups of eight. Disabled channels on output boards are in Tri-State. This is useful for connecting to a user bus. Disabling the outputs has no effect if the board is set up for input.
● Configuration of board memories can vary within a domain. The board with the smallest step capacity limits the available number of vector steps (depth).
● Each Master has a 16-bit external event bus. This bus is used for triggering and synchronization with external events.
● There are three registers A, B and C that can be loaded and compared against external events on the External Event line.
● Triggers can be generated by external events on the Timing connector External Event lines. Event and Mask registers are used to determine both the triggering event and the masking bits to be ignored. These use the D Event and D Mask registers and T Event and T Mask registers.
● External triggering can be initiated on sequential or concurrent events by using both D and T event registers to define events.
● The test sequence (vector) can be paused on external events unconditionally or conditionally. P Event and P Mask registers hold the condition and bits that generate a conditional pause.
● An X Register is used to emulate an external event condition under program control for purposes of test program verification. The register is loaded through the computer bus.
● A DIO domain can be set to have internal or external clock, in order to synchronize with the user UUT.
● A DIO domain clock source (internal or external), active when outputting data, can be programmatically delayed by 0-25 nSec (increments of 5nSec).
● A DIO domain Strobe source (internal or external), active when inputting data, can be programmatically delayed by 0-63.75 nSec (increments of 0.25nSec).
● All boards Firmware, GC5050 and I/O Modules, can be upgraded through the DIO driver.
● The GC5050 is compatible with Marvin Test Solutions’s GT50 and GT25 boards. Test vectors developed for these products also work with the GC5050.
C5050 - Complete View