A GX5150 (Master) controls a DIO domain. External (UUT) timing and control signals terminate only at the Master board.
When a DIO board is programmed, every program step is copied into Master and Slave Control memories. This decentralized architecture assures minimum control latency needed for high-speed response. Step commands execute from local Sequencers simultaneously. Conditional compares are made only at the Master. Comparison results are sent to slaves via the Timing ribbon cable connecting the Timing Module with Slave boards.
Slave Data memories serve to broaden the data path, permitting up to 256 channels of I/O when all seven slaves are used.
The following introductory subtopics provide an overview of important architectural features. Later topics provide additional in-depth discussions.
A GX515x DIO board (see figure below) has two types of memory:
● Control Memory (uses single SIMM).
● Data Memory (uses up to eight SIMMs).
● Both memories must be of the same types.
Note: At least one Data Memory and one Control Memory SIMM are required for board operation. |
DIO SIMMs are organized in 32 bits (4 bytes) wide. SIMM sizes are: 256K by 4 bytes, 1M by 4 bytes, 2M by 4 bytes and 4M by 4 bytes steps. These SIMMs are static RAMs (SRAM) and differ from the dynamic RAMs (DRAM) commonly used in PCs.
Control Memory holds Sequencer instructions. The Sequencer is the key device permitting high-speed test sequencing and flow control.
Users can increase the number of program steps by multiples of 2 or 4 with a proportionate decrease in the number of channels by using software.
For example, consider a DIO board with nine 4M x 32 SIMMs. Eight SIMMs populate the Data Memory. Therefore 32M steps, 32 pins wide, are available by default. The board can be set up for 64M steps in 16-pin mode and 128M steps in 8-pin mode. This flexibility allows users to match UUT bus widths and trade channels for memory depth.
Outputs can be disabled or enabled by software in groups of eight channels during test execution. Channels are numbered from 0 to 31. Groups are fixed blocks. Channels 0 – 7 are treated as a block, as are channels 8 – 15, etc.
All channels are set up as either input (default) or output prior to arming. When the board is halted, direction is changed using driver function. See the DIO Software User Guide for more information. Channel direction cannot be changed while the test is running.
Within a domain, timing and synchronization between boards is crucial. Slaves are synchronized to the Master’s timing. This is implemented by running a ribbon cable from the Master’s Timing Module to each Slave. The Master should be positioned near the domain center to reduce time delay.
The Sequencer in the figure GX515x Architecture Diagram processes commands from control memory. The command code contained within the control memory determines the next action. There are two registers, A and B, which are used to hold memory addresses for looping and branching. Sequencer capability includes branching instructions such as Jump A, Jump B, Pause and Halt. Each instruction can be conditional with External Events or the X-Register.
Supported external flow control features include Trigger, Jump and Pause commands. These also can be made conditional.
Different global output modes are available on Halt. The output vector can be programmed to either hold the last value (default), tri-state (high impedance) or set to zero after a Halt condition.
Data outputs can be set to tri-state high impedance in blocks of eight pins at any time, even while running. This effectively disables outputs and permits bus operation.
The figure below displays a complete GX5150 board with an I/O Module and a Timing Module. This is a Master board that occupies two PXI slots.
The very high density (VHD), 68-pin connector is the UUT data port. This connector has enough pins to accommodate all 32 I/O signal and return lines. A 14-pin, VHD connector provides the I/O control path.
.gif "GX5150 DIO Board (GX5151 with four 256K SIMMs, GX5910, GX5105 and GX5101)")
GX5150 DIO Board (GX5151 with four 256K SIMMs, GX5910, GX5105 and GX5101)
Each GX515x DIO board supports a maximum clock frequency of 50MHz per channel. To use this clock rate, all SIMM modules in the domain must be rated at 50MHz.
Each board contains 32 I/O channels arranged in four groups of eight. Groups can be enabled or disabled internally, either by Sequencer programmed command or by external control.
GX515x DIO board memory can be configured from 256K to 32M steps by 32 pins. The number of bytes ranges from 1M to 128M, depending on the number of SIMMs and SIMM type.
Memory depth (total number of steps) can be configured independently for each board as single, double or quadruple the installed amount while memory width (channels per step) is reduced by the same ratio.
For example, if 128M bytes of Data memory (maximum supported) are installed, it can be configured by software as 32 channels wide by 32M steps deep (default), 16 channels by 64M steps or 8 channels by 128M steps. Each configuration uses 128 Mbytes, the amount of Data memory installed, but the size of each step changed.
Note: The board with least depth limits usable memory depth in a domain. Lower memory capacity DIO boards can be used with higher capacity boards by trading depth for channel width. To optimize available memory this way, use the appropriate driver function calls or the Panel. |
A GX5150 domain functions as a highly complex programmable state machine with three major states: Halt, Pause and Run.
Each board has a sequencer that interprets the commands controlling the machine’s state. Commands are replicated in the Control memory array of each board and are interpreted by the Sequencer. I/O Memory arrays on all domain boards store output or captured data.
The Sequencer permits creation of both conditional and unconditional loops and branches to manipulate output vectors. A Sequencer on each DIO board controls the address of the Control and I/O memory arrays. Thus, Sequencers control program flow while the board is in the Run state. (See the States topic below). Control memory content is replicated across all boards in the domain so each board executes the same instruction simultaneously.
Channel direction can be set to input or output when a domain is in the Halt state. Direction is the same for all channel groups within a board, but can be different for each board in a domain. Channel direction cannot be changed dynamically. However, the channel group drivers are under DIO memory control and can be enabled or disabled while the DIO sequencer is running. Refer to the states section for a description of the Halt state.
Output boards in Halt retain the last value by default. Boards can also be configured for tri-state output instead. Output configuration during Halt is set up with DIOEasy or Driver calls during Halt. See the GX I-O Modules and Interfaces User's Guide (PXI) and the Programmer's Reference User's Guide.
Clock, strobe and output channels may be enabled or disabled externally. External enable, enable/disable control, clocks, strobes and triggers permit DIO to fully synchronize with UUT.