The Test Logic circuit consists of Control Resources and Triggers which are used to provide the sequencer with testable conditions by which a certain action can be taken.
See GtDio6xTrigConfigSetJumpTrigger for more information.
The following trigger functions are supported via PXI triggers (0-7):
● Run sequencer.
● Halt sequencer.
● Pause / resume sequencer ( clutch 1).
● Pause / resume sequencer ( clutch 2).
Once the Trigger source is selected, the Trigger signal can be tested in one of the following ways:
● Low Level.
● High Level.
● Rising Edge.
Falling Edge - there is a Reset Mode that controls how and when the Trigger Resource signal is reset to low:
● Reset at the start of a Burst.
● Reset at the start of a Step.
See GtDio6xTrigConfigSetHaltTrigger, GtDio6xTrigConfigSetRunTrigger, GtDio6xTrigConfigSetStopTrigger for more information.
There are 4 Channel Compare signals (Channel Compare 0 to Channel Compare 3) per DIO board.
A Channel Compare is a configurable, active-low, signal that evaluates the levels of all I/O Channels of a DIO board against an expected pattern and a mask. If the I/O Channel levels (that are not masked out) match the expected pattern, the Channel Compare signal will transition from a high to a low and remain low until the I/O Channel levels no longer match the expected pattern. The Channel Compare 0 signal can be used as a source for the Triggers and Control Resource. All Channel Compares can be connected (provide output) to the Auxiliary Channels of a domain.
See GtDio6xSequencerSetChannelsCompareTrigger for more information.