Major Cycle

The Major Cycle is the DIO-DSR timing sequencing state machine. The Major Cycle has the following inputs/outputs components:

● Input from Trigger/Start/Stop/Flags logic.

● Major Cycle Clock

● Major Cycle Memory (256 by 32-bit wide)

● Major Cycle Loop Vector Logic

● Output Recorder and Generator Strobe signals to Data Memory.

● Output signals to User Strobe Lines (0-7).

● Output signal from User Strobe Line 0 to one of eight PXI Trigger Lines.

Trigger/Start/Stop and Flags logic input

The Major Cycle state machine is controlled by the Trigger/Start/Stop/Flags logic inputs. The two main sets of control signals are:

● Trigger/Start/Stop logic controls the Major Cycle state machine state.

● Flags 0 and 1 logic controls the Major Cycle state machine while running.

The Trigger/Start/Stop events logic controls the Major Cycle state machine different states. According to those signals the Major Cycle state machine will change state. The Flags 0 and 1 logic controls the Major Cycle state machine only when in Run state. See the Major Cycle State Machine section below for details.

Trigger Logic Event

Trigger Logic Event Block Diagram

The Trigger event logic has three main sources the three sources can be divided into two groups:

External.
Internal (software).

External Trigger event source can come from either the PXI Trigger Bus Line or the External Trigger line (J1) combined with Qualifier 0 and 1 (J1).

Trigger from the PXI Trigger Bus can be one of the PXI Trigger Bus Lines (0-7). The specified Bus line is connected using software and can be Enabled\Disabled using software at any time.

Trigger from the External Trigger line is a combination of signal polarity and two input Qualifiers lines. Using software the polarity on which the External Trigger will operate can be set at any time to Positive (rising edge) or Negative (falling edge). The resulted signal is then ANDed with the Qualifiers output logic circuit.

Each of the Qualifiers lines can be set using software to be inverted or not inverted. In addition each of the Qualifiers lines can then be Enabled/Disabled at any time using software. The Enabled/Disabled Qualifiers lines are then fed to the Qualifiers logic circuit. The logic circuit will perform a Boolean AND or Boolean OR on those signals. The type of Boolean operation can be set at any time using software.

Note: When both Qualifiers are disabled then External Trigger is always enabled.

The following table summarizes the Qualifiers logic circuit:

To Wait For	Q0 State	Q1 State	Boolean Function
No Wait	Ignored	Ignored	N/A
Q0	Active High	Ignored	N/A
— Q0	Active Low	Ignored	N/A
Q1	Active High	Active High	N/A
— Q1	Active Low	Active High	N/A
Q1*Q0	Active High	Active High	AND
— Q0*Q1	Active High	Active Low	AND
— Q0*Q1	Active Low	Active High	AND
— — Q0*Q1	Active Low	Active Low	AND
Q0+Q1	Active High	Active High	OR
— Q0+Q1	Active High	Active Low	OR
— Q0+Q1	Active Low	Active High	OR
— — Q0+Q1	Active Low	Active Low	OR

Trigger can be also issued internally using software command. The software command supersedes any of the other trigger sources and is executed immediately.

Start Logic Event

Start Logic Event Block Diagram

The Start event logic has three main sources the three sources can be divided into two groups:

External.
Internal (software).

External Start event source can come from either the PXI Trigger Bus Line or the External Trigger line (J1).

Start event from the PXI Trigger Bus can be one of the PXI Trigger Bus Lines (0-7). The specified Bus line is connected using software and can be Enabled\Disabled using software at any time.

Start event from the External Trigger line polarity can be set at any time to Positive (rising edge) or Negative (falling edge) using software.

Start event can be also issued internally using software command. The software command supersedes any of the other start sources and is executed immediately.

The Start event output is fed to the Major Cycle and also can be connected to one of the PXI Trigger Bus Lines using software. Each PXI Trigger Bus Line can then be Enabled/Disabled at any time using software.

Stop Logic Event

Stop Logic Event Block Diagram

The Stop event logic has five main sources the three sources can be divided into three groups:

External.
Vector Depth (Generator and Recorder)
Internal (software).

External Stop event source can come from either the PXI Trigger Bus Line or the External Trigger line (J1).

Stop event from the PXI Trigger Bus can be one of the PXI Trigger Bus Lines (0-7). The specified Bus line is connected using software and can be Enabled\Disabled using software at any time.

Stop event from the External Trigger line polarity can be set at any time to Positive (rising edge) or Negative (falling edge) using software.

Stop event can be generated when all the Generator and/or Recorder Vectors are done. The number Generator and/or Recorder Vectors are set using software before the Major Cycle is triggered.

Stop event can be also issued internally using software command. The software command supersedes any of the other stop sources and is executed immediately.

The Stop event output is fed to the Major Cycle and also can be connected to one of the PXI Trigger Bus Lines using software. Each PXI Trigger Bus Line can then be Enabled/Disabled at any time using software.

Flags logic

The Flags logic controls the Major Cycle state machine while it’s running. Each step in the Major Cycle Memory may have a Boolean condition to be compared against the two input Flags lines or no condition. For more information see the Major Cycle Memory section.

Available conditions are:

Both Input Flag0 and Flag1 disable –Major Cycle Memory proceed to the next step.
Compare Input Flag0 only (Flag1 disable) – if equal to current step Flag0 level in the Major Cycle Memory proceed to the next step, otherwise wait.
Compare Input Flag1 only (Flag0 disable) – if equal to current step Flag1 level in the Major Cycle Memory proceed to the next step, otherwise wait.
Compare Input Flag0 ORed with Flag1 – if equal to current step Flag0 ORed with Flag1 in the Major Cycle Memory proceed to the next step, otherwise wait.
Compare Input Flag0 ANDed with Flag1 – if equal to current step Flag0 ANDed with Flag1 in the Major Cycle Memory proceed to the next step, otherwise wait.

The following table summarizes the Flags logic circuit:

To Wait For	F0 State	F1 State	Boolean Function
No Wait	Ignored	Ignored	N/A
F0	Active High	Ignored	N/A
— F0	Active Low	Ignored	N/A
F1	Active High	Active High	N/A
— F1	Active Low	Active High	N/A
F1*F0	Active High	Active High	AND
— F0*F1	Active High	Active Low	AND
— F0*F1	Active Low	Active High	AND
— — F0*F1	Active Low	Active Low	AND
F0+F1	Active High	Active High	OR
— F0+F1	Active High	Active Low	OR
— F0+F1	Active Low	Active High	OR
— — F0+F1	Active Low	Active Low	OR

Major Cycle Clock

The Major Cycle Clock source can be software selectable to be Programmable Internal Clock or External Clock. The Programmable Internal Clock can be programmed to any value from near DC to 100MHz. The selected clock can then be additionally divided by a softer programmed divided from 1 to 65536.

Major Cycle Memory

The Major Cycle Memory is 32-byte wide by 256 steps deep. Each Major Cycle Memory step contains the following:

State of each of the eight outputs connected to the User Strobe Outputs lines.
Condition for Flag0 and Flag1.
Generator Clock pattern.
Recorder Strobe pattern.

The memory can be Read/Write through software and can run at frequencies up to 100MHz.

The Major Cycle Memory will be running at the programmed frequency outputting the patterns that were set for the Generator and Recorder clocks. Each transition from low to high in the Generator pattern will generate a single clock. Each transition from low to high in the Recorder pattern will generate a single strobe.

Condition for Flag0 and Flag1 are being evaluated for each step. In case the condition for Flag0 and Flag1 evaluate to be FALSE the Major Cycle will pause until condition is TRUE.

Output signals to User Strobe Lines

Output signals to User Strobe Lines 0 to 7 on the output SCSI timing connector (J1) are set according to the current Major Cycle Memory step.

User Strobe Line to PXI Trigger Lines

Output signal from User Strobe Line 0 on the output SCSI timing connector (J1) can be connected to one of eight PXI Trigger Lines using software. Each of the eight PXI Trigger Lines can be Enabled/Disabled using software at any time. This feature allows the user to setup the connection from Strobe 0 to a specify PXI Trigger line and Enabled/Disabled the connection using software.

Generator/Recorder Data Memory boards

The Major Cycle Controller produces a Recorder and/or Generator Strobe signals to the Data Memory. The Recorder Data Memory is a set of GX5153 boards dedicated to record input data only. Each time that the Major Cycle advances to the next step and if that step location in the Major Cycle Memory contains a High for the Recorder strobe then a single Strobe will be output incrementing the Generator Address Counter. As a result all the GX5153 recorder boards will record a single vector.

The Generator Data Memory is a set of GX5153 boards dedicated to generate output data only. Each time that the Major Cycle advances to the next step and if that step location in the Major Cycle Memory contains a High for the Generator strobe then a single Strobe will be output incrementing the Generator Address Counter. As a result all the GX5153 recorder boards will generate a single vector. Each group of eight channels outputs can be externally disabled/enabled.

The DIO-DSR memory composed of set of static SIMMs modules, these SIMMs are static RAMs (SRAM) and differ from the dynamic RAMs (DRAM) commonly used in PCs. The DIO-DSR SIMMs organized in 32 bits (4-bytes) wide. Available SIMM sizes vary from 256K by 4-bytes up to 4M by 4-bytes steps. Maximum number of memory data SIMMs per board is 8 for a total of 32M steps by 32-bit wide.

In addition each DIO-DSR board has a single memory SIMM for Control data.

Control Memory holds the Enable/Disable data for each group of pins (8 per group) fro each step.

Outputs can be disabled or enabled by software in groups of eight channels during test execution. Channels are numbered from 0 to 31. Groups are fixed blocks. Channels 0 – 7 are treated as a block, as are channels 8 – 15, etc.

All channels are set up as either input (Recorder) or output (Generator) prior to arming. When the board is halted, direction is changed using driver function. See the Software User's Guide for more information. Direction cannot be changed while the test is running.

Within a domain, timing and synchronization between boards is crucial. Slaves are synchronized to the Master’s timing. This is implemented by running a ribbon cable from the Master’s Timing Module to each Slave. The Master should be positioned near the domain center to reduce time delay.

Different global output modes are available on Halt. The output vector can be programmed to either hold the last value (default), tri-state (high impedance) or set to zero after a Halt condition.

Data outputs can be set to tri-state high impedance in blocks of eight pins at any time, even while running. This effectively disables outputs and permits bus operation.

Layout

The very high density (VHD), 68-pin connector is the UUT data port. This connector has enough pins to accommodate all 32 I/O signal and return lines. A 14-pin, VHD connector provides the I/O control path.

Clock and Strobe Rates

Each GX5152 DIO board supports a maximum clock frequency of 50MHz per channel. To use this clock rate, all SIMM modules in the domain must be rated at 50MHz.

Each board contains 32 I/O channels arranged in four groups of eight. Groups can be enabled or disabled internally, either by Sequencer programmed command or by external control.

I/O Direction and Control

Channel direction can be set to input or output when a domain is in the Halt state. Direction is the same for all channels within a board, but can be different for each board in a domain. Channel direction cannot be changed dynamically. However, the channel group drivers are under DIO memory control and can be enabled or disabled while the DIO sequencer is running. Refer to the states section for a description of the Halt state.

Output boards in Halt retain the last value by default. Boards can also be configured for tri-state output instead. Output configuration during Halt is set up with DIOEasy or Driver calls during Halt. See the GX I-O Modules and Interfaces User's Guide (PXI) and the Programmer's Reference User's Guide.

Clock, strobe and output channels may be enabled or disabled externally. External enable, enable/disable control, clocks, strobes and triggers permit DIO to fully synchronize with UUT.