How does the programmable clock delay affect the CLK_LVDS or OCLK signal?

Knowledge Base Article # Q200126

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Summary Does the programmable clock delay apply only to the internal data clock, should either the CLK_LVDS or OCLK should be affected by the programmed delay?
The programmable clock delay (DioSetupClkStrobeDelay) applies to both the internal and external versions of the OCLK; it is the same signal.  OCLK (J3-P22) is derived from an internally generated clock, the delayed version of which actually controls the pattern sequencing.  Because the data is clocked using the delayed OCLK, the phase relationship of Data Out to OCLK is consistent regardless of the delay setting.

The programmable delay has no affect on the CLK_LVDS signal.

See Also:  Q200124
Article Date 12/2/2008
Keywords DIO, Delay, OCLK, CLK_LVDS, Data Out, GX5280 Series, GX5290 Series, DioSetupClkStrobeDelay

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